Method of fabricating a dual-level stacked flash memory cell...

Details Method of fabricating a dual-level stacked flash memory cell... Method of fabricating a dual-level stacked flash memory cell...

2005-10-25

2005-10-25

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S289000

Reexamination Certificate

active

06958271

ABSTRACT:
The present invention relates to methods of fabricating dual-level flash memory cells. A first active region and a second active region are formed in a substrate. A trench is formed in the substrate between the first active region and the second active region. A first insulator dielectric is formed on the substrate and within the trench forming a vertical structure. A first poly layer is formed on the first insulator dielectric. A second insulator dielectric is formed on at least a portion of the first poly layer. A second poly layer is formed on the second insulator dielectric.

REFERENCES:
patent: 5894146 (1999-04-01), Pio et al.
patent: 5923975 (1999-07-01), Rolandi
patent: 6329254 (2001-12-01), Cremonesi et al.
patent: 6493265 (2002-12-01), Satoh et al.
patent: 6818512 (2004-11-01), Hsieh
patent: 2002/0163031 (2002-11-01), Liu et al.
patent: 2003/0007384 (2003-01-01), Shimizu
patent: 2003/0039146 (2003-02-01), Choi

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