Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-10
2001-06-26
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S654000
Reexamination Certificate
active
06251725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory (DRAM) storage node on a semiconductor wafer, and more particularly, to a method of preventing oxidation of a node contact of a DRAM storage node on a semiconductor wafer.
2. Description of the Prior Art
Dynamic random access memory (DRAM) devices are used extensively in the electronics industry for information storage. A high density DRAM, such as a 64 megabit DRAM, comprises millions of memory cells. Each memory cell on the DRAM chip comprises a pass transistor, e.g. a metal-oxide-semiconductor field-effect transistor (MOSFET), and a storage capacitor for storing charge. The storage capacitor comprises a top electrode, a storage node and a capacitor dielectric layer between the top electrode and the storage node. The electric charge is read and written through an access that comprises the storage node and the polysilicon that fills the node contact hole, and also comprises the drain of the MOSFET as well.
In the manufacturing processes for DRAM, an oxidized-silicon nitride-silicon oxide (ONO) process is most commonly used to form the capacitor dielectric layer. However, the phenomenon of grain boundary oxidation of the polysilicon that fills in the node contact hole is usually observed after performing the oxygen-containing ONO process. Oxidation of the polysilicon grains will significantly increase the volume of the polysilicon grains and results in a peeling problem of the storage node. As the dimensions of the node contact hole shrink, and the thickness of the capacitor dielectric layer gets thinner, the problem of grain boundary oxidation becomes more critical for the production yield.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are cross-sectional diagrams of a prior art method of fabricating a DRAM storage node
28
on a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
, a shallow trench
13
positioned on the surface of the silicon substrate
12
and an active area
15
isolated by the shallow trench
13
. The active area
15
comprises two gates
16
adjacent to each other, a source and a drain (S/D)
14
positioned on the surface of the silicon substrate
12
adjacent to the two gates
16
, and a dielectric layer
18
positioned on the surface of the silicon substrate
12
covering the gates
16
. The source and the drain
14
serve as a conductive layer of a MOS transistor. The dielectric layer
18
is composed of silicon oxide.
As shown in
FIG. 2
, a low pressure chemical vapor deposition (LPCVD) process with silane (SiH
4
) as a reacting gas is first used to form a thin-film layer
20
with a thickness of about 2000 angstroms over the dielectric layer
18
. The thin-film layer
20
is composed of amorphous silicon (&agr;-Si). Then, a conventional lithographic process is used to form a hole
21
that penetrates down to the surface of the dielectric layer
18
in the thin-film layer
20
so as to define the location of the node contact hole.
In the prior art method, spacers
23
are formed on the internal walls of the hole
21
in order to fabricate a node contact hole
24
with a dimension below 0.18 micrometers. As shown in
FIG. 3
, the first step of forming the spacer
23
is to deposit an amorphous silicon layer
22
with a thickness of about 400 to 500 angstroms on the surface of the semiconductor wafer
10
. The amorphous silicon layer
22
is uniformly formed on the surface of the dielectric layer
20
, the internal walls of the hole
21
and the bottom of the hole
21
using an LPCVD process.
Next, as shown in
FIG. 4
, an etching back process is performed to remove the amorphous silicon layer
22
from the surface of the dielectric layer
20
and from the bottom of the hole
21
. The remaining portions of the amorphous silicon layer
22
on the internal walls of the hole
21
form the spacers
23
. The spacers
23
and the thin-film layer
20
form a hard mask for the subsequent etching process. An anisotropic dry etching process is performed to etch the dielectric layer
18
that is not covered by the hard mask to the surface of the S/D
14
so as to form a contact hole
24
.
Next, as shown in
FIG. 5
, a conductive layer
26
comprising amorphous silicon and phosphorus is formed on the surface of the semiconductor wafer
10
, filling the contact hole
24
. An LPCVD process, with silane (SiH
4
) and phosphine (PH
3
) as the reacting gasses, is used to form the conductive layer
26
. The thickness of the conductive layer
26
is about 8000 angstroms so that the storage node has a sufficient exposed surface area to store the required electric charge. Then, a conventional lithographic process is performed and a photo resist layer
27
is used to define the location of the storage node
28
.
Next, as shown in
FIG. 6
, a dry etching process is performed to remove the conductive layer
26
, and the thin-film layer
20
, that are not covered by the photo resist layer
27
down to the surface of the dielectric layer
18
. The photo resist layer
27
is then removed, thereby completing the storage node
28
.
After completing the storage node
28
, an ultra-high vacuum chemical vapor deposition (UHV CVD) process follows to form a polysilicon layer
30
with a hemi-spherical grain structure on the exposed surface of the storage node
28
so as to increase the area on the storage node
28
for storing electric charge. In the UHV CVD process, the operating pressure of the vacuum chamber is below 1 torr and the operating temperature is between about 550 to 800 Celsius degrees. Subsequently, an annealing process in a nitrogen atmosphere is used to drive the phosphoric atoms in the storage node
28
into the polysilicon layer
30
. This also transforms the storage node
28
into polysilicon.
Next, an ONO (oxidized-silicon nitride-silicon oxide) process is performed to form a capacitor dielectric layer
32
, with a thickness that is between about 30 to 100 angstroms, over the polysilicon layer
30
. In the ONO process, a native oxide layer (not shown) is first formed on the surface of the polysilicon layer
30
with a thickness of about 10 to 50 angstroms. Then, a plasma-enhanced CVD process, or an LPCVD process, is performed to form a silicon nitride layer (not shown) with a thickness of about 45 angstroms. At that time, a silicon nitride layer
33
with a thickness of about 25 angstroms is formed on the surface of the dielectric layer
18
. Finally, a healing process is performed to form a silicon oxy-nitride layer with a thickness between 40 to 82 angstroms over the silicon nitride layer. The native oxide, the silicon nitride layer and the silicon oxy-nitride layer form the capacitor dielectric layer. The healing process is done in an oxygen-containing atmosphere at about 800 Celsius degrees for approximately 30 minutes. The silicon oxy-nitride layer is used to reduce the leakage current that results from defects in the silicon nitride layer.
In general, the charge storage capacity of a DRAM capacitor can be increased in several ways, including:
1. Choosing a material that has a high dielectric constant to form the capacitor dielectric layer
32
.
2. Reducing the thickness of the capacitor dielectric layer
32
.
3. Increasing the surface area of a capacitor.
Consequently, reducing the thickness of the silicon nitride layer in the capacitor dielectric layer
32
results in a better charge storage capacity of a DRAM capacitor.
However, reducing the thickness of the silicon nitride layer in the capacitor dielectric layer
32
will also reduce the thickness of the silicon nitride layer
33
formed on the surface of the dielectric layer
18
. A thin silicon nitride layer
32
on the surface of the dielectric layer
18
with a thickness that is less than 25 angstroms is not able to prevent oxygen from diffusing into the dielectric layer
18
during the ONO process. Oxygen diffused into the dielectric layer
18
will cause serious polysilicon grain boundary
Chiou Jung-Chao
Wang Chuan-Fu
Wu Te-Yuan
Brewster William M.
Fahmy Wael
Hsu Winston
United Microelectronics Corp.
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