Method of fabricating a DRAM semiconductor device

Details Method of fabricating a DRAM semiconductor device Method of fabricating a DRAM semiconductor device

2002-05-17

2003-10-28

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S637000, C438S639000, C438S675000

Reexamination Certificate

active

06638805

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device. More particularly, the present invention relates to a method of fabricating a dynamic random access memory (DRAM) semiconductor device.
2. Description of the Related Art
Generally, decreasing a design rule results in a reduction in the gate length of a DRAM semiconductor device. In order to maintain a threshold voltage in a cell transistor having a shortened gate length, the amount of channel stop impurities to be implanted in a semiconductor substrate must be increased. However, increasing the channel stop impurity dose may cause ion implantation damage resulting in increased current leakage. Furthermore, reducing the gate length causes short channel effects.
Conventionally, these problems have been addressed by forming a source/drain region having a lightly doped drain (LDD) structure and by forming a contact hole by a self-aligned contact (SAC) method. To explain these procedures more fully, a conventional method of fabricating a DRAM semiconductor device adopting the LDD structure and the SAC method will now be described with reference to
FIGS. 1 through 4
.
FIGS. 1 through 3
illustrate cross-sectional views of steps in a conventional method of fabricating a DRAM semiconductor device.
FIG. 4
shows a cell region layout of the conventional DRAM semiconductor device shown in FIG.
3
. Like reference numerals in
FIGS. 1 through 4
represent like elements.
Referring to
FIG. 1
, a shallow trench isolation (STI) region
11
is formed on a semiconductor substrate
10
, which divides the semiconductor substrate
10
into two portions, i.e., a non-active region, in which the STI region
11
is formed, and an active region. The semiconductor substrate
10
will be later defined by a cell region (CA), in which a memory cell is formed, and a core/peripheral circuit region (PA).
Subsequently, channel stop impurities are ion-implanted into the entire semiconductor substrate
10
having the STI region
11
to control a threshold voltage of a transistor. If the semiconductor substrate
10
is a p-type silicon substrate, boron is used as the channel stop impurity.
Then, a gate stack
18
is formed on the semiconductor substrate
10
having the STI region
11
. The gate stack
18
includes a gate insulating layer
12
, a gate conductive layer
14
and a capping layer
16
. The gate insulating layer
12
, the gate conductive layer
14
and the capping layer
16
are formed from a silicon oxidation layer, a double layer of a poly-silicon layer and a metal silicide layer, and a silicon nitride layer, respectively.
Next, the semiconductor substrate
10
is lightly doped with impurities to form a first impurity region
20
around the gate stack
18
. A gate spacer
22
is formed from a silicon nitride layer along sidewalls of the gate stack
18
. Then, the semiconductor substrate
10
is more heavily doped with impurities than the first impurity region
20
to form a second impurity region
24
between the gate spacers
22
. A source/drain region having a lightly doped drain (LDD) structure results from the doping concentrations of the first and second impurity regions
20
and
24
.
Thereafter, an interlevel dielectric layer
26
is formed of a silicon oxide layer on the entire semiconductor substrate
10
to fill gaps between the gate spacers
22
. Then, a self-aligned contact pattern
28
is formed on the interlevel dielectric layer
26
using photoresist.
Referring to
FIG. 2
, the interlevel dielectric layer
26
is self-aligned contact etched to be aligned with respect to the gate spacers
22
using the self-aligned contact pattern
28
as an etching mask, thereby forming a contact hole
30
for exposing the second impurity region
24
. When the interlevel dielectric layer
26
is self-aligned contact etched, the interlevel dielectric layer
26
, made of the silicon oxide layer, has a higher etching selectivity than the gate spacer
22
, made of a silicon nitride layer. Accordingly, the contact hole
30
may be formed to be aligned with respect to the gate spacer
22
.
Referring to
FIG. 3
, the self-aligned contact pattern
28
is removed. Next, a conductive layer (not shown as an independent layer) for a contact pad is formed on the entire semiconductor substrate
10
to completely fill the contact hole
30
. Then, the resultant structure is etched by chemical-mechanical polishing (CMP) using the surface of the interlevel dielectric layer
26
as an etch stopping point, i.e., the CMP is performed until the surface of the interlevel dielectric layer
26
is exposed, thus forming contact pads
32
a
through
32
c
. Here, contact pad
32
b
is a direct contact (DC) pad, later to be connected with a bit line, and contact pads
32
a
and
32
c
are buried contact (BC) pads, later to be connected to a storage electrode.
In a conventional method of fabricating a DRAM semiconductor device adopting the LDD structure and the self-aligned contact (SAC) method, the width of the gaps between the gate stacks
18
is narrowed by gate spacers
22
formed from a silicon nitride layer. Accordingly, when the interlevel dielectric layer
26
shown in
FIG. 1
is formed, a void may occur in the region between the gate stacks
18
. Reference character X in
FIG. 4
indicates the portion wherein a void occurs. Subsequent to the occurrence of a void in the interlevel dielectric layer
26
, a conductive layer for forming a contact pad is formed over the X portion, thereby causing a bridge between the contact pads
32
. For this reason, it is impossible to use the SAC method when forming contact hole
30
. Further, it is difficult to maintain a constant threshold voltage of a cell transistor in a conventional DRAM semiconductor device having an LDD structure without increasing the dose of the channel stop impurities.
SUMMARY OF THE INVENTION
It is a feature of an embodiment of the present invention to provide a method of fabricating a DRAM semiconductor device having an LDD structure for maintaining a threshold voltage, and in which the SAC method may be used, while reducing or minimizing an increase in a channel stop impurity dose.
To provide this and other features of the present invention, there is provided a method of fabricating a DRAM semiconductor device as a first embodiment of the present invention. In the method of the first embodiment of the present invention, gate stacks, in which a gate pattern and a gate sacrificial mask are sequentially deposited, are formed on a semiconductor substrate defined by a non-active region and an active region. The gate sacrificial mask may be formed from a silicon nitride layer. Then, an etch stopper is formed on the entire semiconductor substrate to surround the gate stacks. The etch stopper may also be formed of a silicon nitride layer.
Next, a lightly doped impurity region is formed between the gate stacks on the semiconductor substrate. The lightly doped impurity region is an N− impurity region when the semiconductor substrate is a p-type silicon substrate. Thereafter, a gate spacer is formed along sidewalls of the gate stacks. The gate spacer may also be formed from a silicon nitride layer.
Then, a heavily doped impurity region is formed to contact the lightly doped impurity region and to be aligned with respect to the gate spacer, thereby obtaining an LDD structured source/drain. The heavily doped impurity region is an N+ impurity region when the semiconductor substrate is a p-type silicon substrate.
Next, the gate spacer formed along the sidewalls of the gate stacks is removed. After removal of the gate spacer, an interlevel dielectric layer, which fills a gap between the gate stacks but leaves a top surface of the etch stopper exposed, is formed. Then, a groove is formed on a gate conductive layer constituting the gate stack by etching, preferably isotropically, the exposed top surface of the etch stopper and the gate sacrificial mask. When forming the groove, it is preferable that the groove has a width g

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