Method of fabricating a DRAM cell with an area equal to four tim

Details Method of fabricating a DRAM cell with an area equal to four tim Method of fabricating a DRAM cell with an area equal to four tim

1997-05-15

1998-08-11

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438268, H01L 218242

Patent

active

057926905

ABSTRACT:
A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.

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patent: 5376575 (1994-12-01), Kim et al.
patent: 5432739 (1995-07-01), Pein
patent: 5451538 (1995-09-01), Fitch et al.
patent: 5691550 (1997-11-01), Kohyama

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