Method of fabricating a DRAM cell capacitor

Details Method of fabricating a DRAM cell capacitor Method of fabricating a DRAM cell capacitor

2002-04-19

2003-03-25

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S249000, C438S387000, C438S665000

Reexamination Certificate

active

06537872

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor memory cells, more particularly, to a method of forming a trenched capacitor for a dynamic random access memory (DRAM) cell.
2. Description of the Related Art
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one, or vice versa. The surface area of the electrodes of the memory capacitors determine the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased quantities of data storage on a single chip. To address the challenges of reduced structure sizes, DRAM designs have been proposed which incorporate capacitors having vertical extensions above the surface of the substrate (“stacked” capacitors) or below the surface of the substrate (“trenched” capacitors). By adopting a more three-dimensional structure, such DRAM designs provide memory capacitors having larger capacitance but which consume less of the substrate surface area.
FIGS. 1A
to
1
H, are cross-sections showing the manufacturing steps of fabricating a capacitor of a DRAM cell in accordance with the prior art.
Referring now to
FIG. 1A
, a semiconductor substrate
100
, for example a p-type silicon substrate, is provided. A pad oxide
102
, having a thickness of 400 angstroms, is grown on the upper surface of the semiconductor substrate
100
by thermal oxidation. A pad nitride
104
, having a thickness of 1600 angstroms, is deposited on the pad oxide
102
. Next, a silicon glass
108
such as boro-silicate glass (BSG), having a thickness of 5000 angstroms, is deposited by an in-situ doped chemical vapor deposition system. The silicon glass
108
, pad nitride
104
, and pad oxide
102
are defined by conventional photolithography so that an etching mask EM having an opening for deep trench is formed on the semiconductor substrate
100
. Symbol
107
indicates a hard mask consisting of the pad nitride
104
and the pad oxide
102
.
Referring now to
FIG. 1B
, the semiconductor substrate
100
is anisotropically etched through the opening of the etching mask EM to form a deep trench
112
. Then, the silicon glass
108
is removed to expose the pad nitride
104
by an isotropic etching step. The deep trench
112
has a top portion TP, and a bottom portion BP.
As shown in
FIG. 1C
, a conductive layer
114
, having a thickness of 50 to 400 angstroms, is deposited on the hard mask
107
and extended on the deep trench
112
by in-situ doped chemical vapor deposition. The conductive layer
114
can be a semiconductor material doped with arsenic ions.
Referring now to
FIG. 1D
, a photoresist
122
is formed in the bottom portion BP of the deep trench
112
to expose the conductive layer
114
at the top portion TP of the deep trench
112
. Next, the exposed conductive layer
114
is removed followed by stripping the photoresist
122
as shown in FIG.
1
E. An insulating layer
126
is formed on the pad nitride
104
and the deep trench
112
to cover the conductive layer
114
. The arsenic ions formed in the conductive layer
114
are diffused and driven in the semiconductor substrate
100
so as to form a doped area having a depth of about 800 angstroms to serve as the lower electrode
130
of the capacitor. The insulating layer
126
is then removed.
As shown in
FIG. 1F
, a dielectric layer
132
, for example silicon oxide/silicon nitride/silicon oxide (ONO), is formed on the conductive layer
114
. Next, a doped polysilicon, to serve as the upper electrode
142
of the capacitor, is deposited on the dielectric layer
132
by low pressure chemical vapor deposition (LPCVD) followed by etching back. The dielectric layer
132
and the upper electrode
142
are also formed at the bottom portion BP of the deep trench
112
.
Referring to
FIG. 1G
, a ringed insulating layer
160
is formed adjacent to the conductive layer
114
at a part of the top portion TP. Then, a conductive structure
164
whose upper surface is higher than that of the ringed insulating layer
160
is formed on the upper electrode
142
and the dielectric layer
132
.
Next, a doped polysilicon film
166
, having a thickness of about 600 angstroms, is deposited on the conductive structure
164
and the ringed insulating layer
160
. The doped polysilicon film
166
has dopants such as phosphorus ions or arsenic ions therein. Next, an insulating layer
170
, having a thickness of about 500 angstroms, is formed on the doped polysilicon film
166
. The dopants of the doped polysilicon film
166
are then diffused and driven in the semiconductor substrate
100
at the top portion TP so as to form a doped region
172
to serve as the source region.
As shown in
FIG. 1H
, the hard mask
107
is removed. Shallow trench isolation
180
for defining an active region
186
, gate oxides
184
, and word lines
188
are then formed by conventional skills.
A higher level of integration, however, requires a proportional reduction in the area of the conducting elements of the capacitor in the DRAM cell, thus resulting in lower capacitance. The reliability of the data stored on the capacitor in the DRAM cell is therefore reduced. There is a need for providing a method of fabricating a capacitor, which has high capacitance.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of fabricating a capacitor of a DRAM cell. According to the method, the lower electrode of the capacitor has rugged surface thus increasing the capacitance.
In accordance with an aspect of the invention, there is provided a method of fabricating a capacitor of a DRAM cell. First, a semiconductor substrate is provided. Then, an etching mask with an opening is formed on the semiconductor substrate. The semiconductor substrate is then etched through the opening of the etching mask to form a trench having a top portion and a bottom portion. Next, a ringed insulating layer is formed on the semiconductor substrate at the top portion of the trench. Afterward, a seed layer on the ringed insulating layer and the semiconductor substrate at the bottom portion of the trench. A photoresist is coated in the trench at the bottom portion. Next, the seed layer is partially removed to expose the ringed insulating layer while the photoresist is used as the shield. The photoresist is then removed to expose the remaining seed layer at the bottom portion. A hemispherical silicon grain layer is deposited from the remaining seed layer on the semiconductor substrate. Ions are doped and driven into the hemispherical silicon grain layer and the semiconductor substrate so as to create a do

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