Method of fabricating a DRAM capacitor

Details Method of fabricating a DRAM capacitor Method of fabricating a DRAM capacitor

1998-12-04

2001-02-13

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S398000

Reexamination Certificate

active

06187629

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Ser. No. 87115563, filed Sep. 18, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a dynamic random access memory (DRAM) capacitor.
2. Description of the Related Art
FIG. 1
is a memory cell of a DRAM device including a transfer transistor T and a storage capacitor C. The source region of the transfer transistor T is coupled to a corresponding bit line BL, the drain region is coupled to a storage capacitor
100
of the storage capacitor C and the gate electrode is coupled to a corresponding word line WL. An opposite electrode
102
of the storage capacitor C is coupled to a fixed voltage. A dielectric layer
104
is situated between the storage electrode
100
and the opposite electrode
102
.
A schematic, cross-sectional view of a conventional DRAM capacitor is shown in FIG.
2
. Isolation structures and word lines (not shown) are formed on a substrate
200
and word lines are isolated with the bit lines
204
by dielectric layers
202
a
,
202
b
formed on the substrate
200
. A node contact window
205
is formed within the dielectric layer
202
a
,
202
b
and a polysilicon layer is deposited in the node contact window
205
. The polysilicon layer is then patterned by photolithography to form a lower electrode
206
of a capacitor.
Since the design rule for semiconductors is reduced, the width for exposure and alignment of the node contact window
205
becomes narrower. The width of the node contact window
205
is also restricted by the resolution of the exposure light source, so that it is necessary to reduce the size of the node contact window
205
.
A selective HSG-Si
208
is always deposited on the lower electrode
206
to increase the surface area of the lower electrode
206
. In order to form the selective HSG-Si, an amorphous silicon layer needs to be formed as a substitute for the polysilicon layer
206
and to serve as the lower electrode of the capacitor. But the deposition rate of the amorphous silicon layer is slower than that of the polysilicon layer, such that the throughput of the product is reduced and the demands for product competition can not be satisfied.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to increase the available exposure range of the node contact window to reduce misalignment error, and so that the width of the node contact window can be reduced.
It is therefore another object of the invention to decrease the thickness of the amorphous silicon layer and still increase the surface area of the lower electrode, so that the cost of the product can be reduced and the yield is improved.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a DRAM capacitor. A conductive layer and an amorphous silicon layer are formed on a substrate having a dielectric layer. The amorphous silicon layer and the conductive layer are etched to form a region of a capacitor to expose a portion of the dielectric layer. An opening with a profile having a wider upper portion and narrow lower portion is formed within the conductive layer, and through the opening, the dielectric layer is then etched through to form a node contact window to expose the substrate. An amorphous silicon spacer is formed on the sidewall of the conductive layer in the region of the capacitor and fills the node contact window. A selective HSG-Si, a dielectric layer and a polysilicon layer are formed to complete capacitor fabrication. The conductive layer, the amorphous silicon layer and the HSG-Si serve as a lower electrode of the capacitor and the polysilicon layer serves as an upper electrode of the capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5684331 (1997-11-01), Jun

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