Method of fabricating a DRAM capacitor

Details Method of fabricating a DRAM capacitor Method of fabricating a DRAM capacitor

1999-02-18

2001-04-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06218243

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a capacitor, and more particularly to a method of fabricating a 3-D capacitor of dynamic random access memory (DRAM).
2. Description of the Related Art
The lower electrode and the upper electrode of DRAM capacitor normally use polysilicon to serve as conductive material. However, the V
bias
applied on the upper electrode easily causes holes to form between the lower electrode and the capacitor dielectric layer. The holes compensate N-type impurities originally doped inside the polysilicon layer serving as a lower electrode. Consequently, a depletion region is formed on the upper surface of the lower electrode, thus forming an additional dielectric layer. In other words, the thickness of the overall dielectric layer is thickened, the surface of the capacitor dielectric layer is decreased and the charge storage capacity of the capacitor is reduced.
The depletion effect can be reduced by increasing the surface doping concentration of the lower electrode. In the traditional method, an ion implantation step is performed on the lower electrode, thereby implanting ions into the lower electrode to increase the surface doping concentration of the lower electrode. However, it is difficult for this method to solve the depletion problem occurring on the sidewall of the capacitor if a high, 3-D, stacked capacitor or a selective Hemisphere Grain (HSG) is used. This is because the implanted ions can barely reach the sidewall of the capacitor under the limitations of the implant angle and the shadowing effect. Therefore, the ion implantation to increase the surface doping concentration cannot thoroughly solve the depletion problem. In addition, the doping concentration on the lower electrode is not uniform, which leads to an unstable charge storage capacity of the capacitor. As a result, the reliability of the capacitor is reduced.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved method of fabricating a DRAM capacitor, thereby solving the depletion problem.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards an improved method of fabricating a DRAM capacitor. An insulated layer, an etching stop layer and an oxide layer are successively formed on a substrate at least having word lines formed thereon. A contact window is then formed within the oxide layer, the etching stop layer and the insulated layer by definition. A patterned amorphous Si is formed on the amorphous Si and fills the contact window. A selective HSG is then formed on the patterned amorphous Si, and the patterned amorphous Si and the selective HSG serve as a lower electrode of the capacitor. A highly doped dielectric layer is formed over the substrate and an annealing process is performed to diffuse the impurities inside the highly doped dielectric layer into the lower electrode. Therefore, the impurities uniformly distribute into the surface of the lower electrode and the depletion problem can be overcome. The dielectric layer and the oxide layer are then removed. Thereafter, a capacitor dielectric layer and a conductive layer serving as an upper electrode of the capacitor are successively formed on the lower electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5960293 (1999-12-01), Hong et al.
patent: 6004858 (1999-12-01), Shim et al.

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