Method of fabricating a dielectric layer

Details Method of fabricating a dielectric layer Method of fabricating a dielectric layer

2000-09-11

2002-12-17

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S785000, C438S520000, C438S514000

Reexamination Certificate

active

06495474

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductors, generally, and more particularly to a method of fabricating a dielectric layer.
BACKGROUND OF THE INVENTION
A significant commercial effort has been expended on the miniaturization of semiconductor devices. With device sizes shrinking, increased attention has been paid to dielectric layers. In a field effect transistor (“FET”), such as a metal oxide semiconductor FET (“MOSFET”), a dielectric layer insulates a gate electrode from a channel formed within a semiconductor substrate.
Referring to
FIG. 1
, a cross sectional view of a known MOSFET
10
configuration is illustrated. MOSFET
10
comprises a channel
30
formed within a semiconductor substrate
20
. Fabricated above channel
30
is a gate electrode
70
. Channel
30
has an impedance, which may be changed in response to a voltage applied to gate electrode
70
. Channel
30
is electrically connected to a source
40
and a drain
50
. If a voltage difference is applied between source
40
and drain
50
, a current may flow through channel
30
. By modifying the impedance of channel
30
through the voltage applied to gate electrode
70
, the amount of current flowing through channel
30
may be controlled.
Formed between channel
30
and gate
70
is a gate dielectric layer
60
. Gate dielectric layer
60
has insulative properties, characterized by a dielectric constant, k. Gate dielectric layer
60
comprises silicon dioxide. Gate dielectric layer
60
enables the formation of a capacitance between channel
30
and gate electrode
70
.
As the distance separating source
40
and drain
50
continues to shrink with the scaling of semiconductor devices, industry has been forced to examine ways to increase the capacitance between channel
30
and gate electrode
70
. The capacitance between channel
30
and gate electrode
70
inhibits the creation of leakage currents between channel
30
and gate electrode
70
, as well as between source
40
and drain
50
. By increasing the capacitance between channel
30
and gate electrode
70
, the potential for creating these leakage currents is substantially reduced.
The channel to gate electrode capacitance has an inverse relationship with the thickness of gate dielectric layer
60
—the thinner the gate dielectric layer, the higher the capacitance. The channel to gate electrode capacitance also has a direct relationship with the dielectric constant of gate dielectric layer
60
—the higher the dielectric constant, the higher the capacitance. As such, the capacitance between channel
30
and gate electrode
70
may be increased by either reducing the thickness of gate dielectric layer
60
or by increasing the dielectric constant of gate dielectric layer
60
.
To date, industry has been able to form a gate dielectric layer from silicon dioxide having a thickness of 25 Å. It is believed that as semiconductor scaling continues, however, the material limitations of silicon dioxide will inhibit its use as a gate dielectric layer. At a thickness of 15 Å, silicon dioxide is approximately six (6) atomic layers thick. Practical considerations in employing a gate dielectric layer formed of silicon dioxide having a thickness of approximately six (6) atomic layers include the propensity of leakage currents to tunnel through the gate dielectric layer and damage the MOSFET. Realizing the limitations of silicon dioxide, researchers have begun to examine alternate materials having higher dielectric constants than the dielectric constant of silicon dioxide to increase the channel to gate electrode capacitance.
One group of alternative materials being explored is metal-silicon oxynitrides. In U.S. Pat. No. 6,020,243, issued on Feb. 1, 2000 to Wallace et al. (hereinafter “Wallace”), a method of fabricating a gate dielectric layer comprising a metal-silicon oxynitride is disclosed. Wallace proposes forming a dielectric layer comprising silicon-oxynitride in combination with titanium (Ti), zirconium (Zr), or hafnium (Hf) by a deposition step. It appears that the method of Wallace, however, produces a sub-optimal gate dielectric layer having a varying thickness of approximately 40-50 Å.
Another group of alternative materials being explored is metal silicates. In U.S. Pat. No. 5,907,780, issued on May 25, 1999 to Gilmer et al. (hereinafter “Gilmer”), a method of fabricating a gate dielectric layer comprising a metal silicate is disclosed. Gilmer proposes a gas cluster ion implantation step for implanting silicon atoms into a metal-oxide gate dielectric layer. This gas cluster ion implantation step, however, requires supercooling a gas from which clusters of silicon atoms to be ionized are formed. The method of Gilmer, thus, raises issues regarding cost effectiveness.
Consequently, a need remains for a cost-effective method of fabricating a gate dielectric layer having a dielectric constant, k, greater than the dielectric constant of silicon dioxide.
SUMMARY OF THE INVENTION
We have invented a cost-effective method of fabricating a dielectric layer having a dielectric constant, k, greater than the dielectric constant of silicon dioxide, silicon oxynitride, as well as a silicon-oxide-silicon nitride stack.
Our method comprises an ion implantation step for implanting a transition metal into a dielectric layer. The transition metal is selected from a group consisting of Zr, Hf, La, Y, Al, Ti, Ta, and combinations thereof, while the dielectric layer is selected from the group consisting of silicon dioxide, silicon oxynitride and silicon-oxide-silicon nitride.
In an embodiment of the present invention, our ion implantation step is performed such that the transition metal atoms are substantially contained within the dielectric layer.
In another embodiment of the present invention, an anneal step is performed on the implanted dielectric layer. This anneal step allows for a more uniform distribution of the transition metals in the dielectric layer. The anneal step also corrects damage to the implanted dielectric layer. The implantation of metal ions into the dielectric layer creates dangling bonds. Dangling bonds are defined as broken or incomplete chemical bonds between atoms of the dielectric layer. By annealing the implanted dielectric layer, these dangling bonds are reformed.
These and other advantages, objects and embodiments will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.


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