Method of fabricating a deep trench capacitor

Details Method of fabricating a deep trench capacitor Method of fabricating a deep trench capacitor

2001-01-05

2001-12-04

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S248000, C438S249000, C438S386000

Reexamination Certificate

active

06326261

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a capacitor of a dynamic random access memory (DRAM) cell, and more particularly, to a method of fabricating a deep trench capacitor.
2. Description of the Prior Art
A memory cell of a DRAM is composed of a metal oxide semiconductor (MOS) transistor connected to a capacitor. The MOS transistor comprises a gate, and a first and second doped region. The two doped regions are identical in structure and are used as a source or a drain depending on the operational situation of the MOS transistor. The MOS transistor functions by using the gate electrically connected to a word line as a switch, using the source electrically connected to a bit line as a current transporting path, and using the drain electrically connected to a storage node of the capacitor to complete data accessing.
The capacitor, composed of a top electrode, a capacitor dielectric layer and a storage node, is formed on a silicon oxide layer over a substrate. In a present DRAM process, the capacitor is designed as either a stack capacitor stacked on the substrate or a deep trench capacitor buried within the substrate.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are schematic diagrams of a method of fabricating a DRAM deep trench capacitor. As shown in
FIG. 1
, a pad stack
14
composed of a silicon nitride layer and a pad oxide layer is formed on a substrate
12
of a semiconductor wafer
10
. A photoresist layer (not shown) is formed on the surface of the pad stack
14
. Next, a photolithographic process and etching process are performed to form an opening
16
in the pad stack
14
to define the position of the deep trench.
As shown in
FIG. 2
, an etching process is performed using the pad stack
14
as a mask to etch the opening
16
down to the substrate
12
to form a deep trench
18
with a depth of 7~7.5 micrometers (&mgr;m). Subsequently, an arsenic silicate glass (ASG) diffusion method is used to form a N-doped buried plate
20
as a top plate of the capacitor within the substrate
12
and beneath the deep trench
18
.
As shown in
FIG. 3
, a chemical vapor deposition (CVD) process is performed to form a silicon nitride layer (not shown) on the surface of the deep trench
18
. Next, a thermal oxidation process is performed to grow an oxide layer (not shown) on the silicon nitride layer, so that the silicon nitride layer together with the oxide layer form a capacitor dielectric layer
22
. Next, a N-doped polysilicon layer
24
is deposited into and completely fills in the deep trench
18
, to function as a primary conductor of the storage node. A planarization process, such as a chemical mechanical polishing or an etching back process, is performed using the pad stack
14
as a stop layer to remove portions of the doped polysilicon layer
24
and align its surface with the pad stack
14
.
As shown in
FIG. 4
, a first polysilicon recess etching process is performed to etch the doped polysilicon layer
24
down to the surface of the substrate
12
. A wet etching process is then performed, using phosphoric acid (H
3
PO
4
) as the etching solution, to remove half the depth of the capacitor dielectric layer
22
so as to expose the area of the substrate
12
in the upper region of the deep trench
18
.
As shown in
FIG. 5
, another thermal oxidation process is performed to form a pair of collar oxides
26
, with a thickness of 200~300 angstroms (Å), on the exposed substrate
12
in the upper region of the deep trench
18
. A N-doped polysilicon layer
27
is deposited on the surface of the semiconductor wafer
10
and fills in the deep trench
18
, followed by a planarization process to remove portions of the doped polysilicon layer
27
and approximately align the surface of the doped polysilicon layer
27
with that of the pad stack
14
. A second polysilicon recess etching process is performed to etch back portions of the doped polysilicon layer
27
and lower the surface of the remaining doped polysilicon layer
27
down to the surface of the collar oxides
26
.
As shown in
FIG. 6
, an etching process is performed to remove portions of the collar oxides
26
so as to expose the substrate
12
in the deep trench
18
. A CVD process is then performed to deposit an undoped polysilicon layer
28
on the semiconductor wafer
10
. Next, a planarization process is performed using the pad stack
14
as a stop layer to remove portions of the undoped polysilicon layer
28
and approximately align the surface of the remaining undoped polysilicon layer
28
with that of the pad stack
14
. A third polysilicon recess etching process is performed to etch back the undoped polysilicon layer
28
and lower its surface down to the pad stack
14
. Finally, the pad stack
14
is completely removed to finish the fabrication of the storage node.
In the prior method, a phase-in polysilicon filling is used to fabricate the storage node, which requires a three-time repeated operational cycle of deposition, planarization and recess etching processes. Thus, it not only complicates the fabrication process but also increases both production cost and time.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of fabricating a deep trench capacitor to simplify the production process.
In a preferred embodiment, the present invention provides a method of fabricating a deep trench capacitor. Firstly, a deep trench is formed in a silicon substrate. Then, a buried plate is formed in the silicon substrate beneath the deep trench. A silicon nitride layer is then formed on the surface of the deep trench above the buried plate. An oxidation process is performed to simultaneously form a first oxide film on the silicon nitride layer and a second oxide film on the silicon substrate within the deep trench. A doped polysilicon layer is formed in the deep trench with a lower surface down to the surface of the substrate. Finally, a portion of the second oxide film is removed to expose the substrate in the upper region of the deep trench, followed by the filling in of an undoped polysilicon layer into the deep trench to finish the fabrication process of the capacitor.
It is an advantage of the present invention that a first oxide film on the silicon nitride layer, and a second oxide film on the exposed substrate in the upper region of the deep trench are simultaneously formed. The first oxide film combines with the silicon nitride layer to form a silicon nitride-oxide (NO) capacitor dielectric layer while the second oxide film functions as a collar oxide film. Then, a polysilicon layer is deposited to fill in the deep trench to complete the capacitor structure. The present invention does not require the phase-in polysilicon filling process of the prior method used prior to and proceeding the formation of the collar oxide layer, which simplifies the fabrication of the deep trench capacitor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 6117726 (2000-09-01), Tsai et al.
patent: 6281069 (2001-08-01), Wu et al.

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