Method of fabricating a deep source/drain

Details Method of fabricating a deep source/drain Method of fabricating a deep source/drain

2000-01-21

2002-03-19

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000

Reexamination Certificate

active

06358803

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to integrated circuits incorporating transistors with deep source/drain junctions, and to methods of fabricating the same.
2. Description of the Related Art
One variant of a basic conventional metal oxide semiconductor (“MOS”) transistor consists of a gate electrode stack fabricated on a lightly doped semiconductor substrate. The gate stack consists of a gate dielectric layer and a gate electrode. A source region and a drain region are formed in the substrate beneath the gate dielectric layer and separated laterally to define a channel region. The gate electrode is designed to generate an electric field into the channel region. Changes in the electric field generated by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain. In many processes, the source/drain regions consist of a lightly doped drain (“LDD”) and an overlapping heavier doped region. The source/drain regions are electrically isolated laterally from adjacent conducting structures by isolation structures such as insulating trenches or field oxide regions.
Modern integrated circuits frequently incorporate millions of individual transistors. Most of the interconnections for the individual transistors are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required. In addition to the one or more metallization layers, modern integrated circuits also incorporate numerous routing-restricted interconnect levels commonly known as local interconnect (“LI”). LI's are used for short metallization runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit. The resistivity of direct metal-to-silicon contacts is frequently less than optimal for desired device performance. To improve the resistivity of these silicon-based structures, a metal silicide layer is frequently formed on the substrate overlying the source/drain regions. If the gate electrode is silicon based, the silicide is formed there as well.
Switching speed is a primary indicator of MOS device performance. The switching speed of MOS transistors is affected by a variety of mechanisms, such as the channel transit time, i.e., the time required for a charge to be transported across the channel. However, the predominant mechanism affecting device speed is the time required to charge and discharge the various capacitances that exist between device electrodes and between interconnecting lines and the substrate. At the circuit level, the propagation delays are frequently limited by the interconnection-line capacitances and resistances. At the device level, however, the gate delay is determined primarily by the channel transconductance, the MOS gate capacitance and the parasitic or junction capacitances between the source/drain regions and the body, that is, the substrate or the well in circuits utilizing doped wells. Reductions in any or all of these capacitance values can result in increases in the device switching speed.
The gate capacitance of a MOS transistor may be reduced by decreasing the gate area, although this decrease is offset somewhat by a corresponding necessary reduction in the thickness of the gate dielectric layer. However, a dominant parasitic capacitance affecting the switching speed of a typical MOS transistor is the junction capacitance. Tailoring junction capacitance involves a careful balancing of competing design considerations. As a general rule, lower doping levels in the substrate or body translate into lower junction capacitances. Indeed, obtaining maximum circuit performance from a MOS device involves maximizing the drive current and minimizing junction capacitances and body effect, all of which favor lower doping concentrations in the device body. However, competing design considerations, such as optimizing packing density, favors raising the same doping concentrations to avoid punchthrough and to achieve high field thresholds.
One disadvantage associated with conventional MOS transistor fabrication is the potential for the fabrication of abrupt pn junctions. The source/drain regions of a MOS device are normally heavily doped to minimize their resistivities. In processes utilizing ion implantation, this heavy doping concentration is normally achieved by performing a relatively high dosage, low energy implant. In a p-channel device, this type of implant produces a relatively steep tail-off in the p+ doping concentration at the pn junction. This rather steep dopant gradient results in a relatively high junction capacitance, particularly in view of the much lighter doping level at the n+ or n-well side of the pn junction.
One conventional technique for attempting to reduce the doping gradient in the vicinity of the pn junction involves performing an additional source/drain implant to a much greater depth than the LDD and heavier doped region source/drain implants. The difficulty associated with this method is the fact that the high energy necessary to achieve a sufficient depth for the implant gives rise to a correspondingly high potential for impurity ions to bore through the gate electrode, particularly polysilicon gate electrodes, and either corrupt the doping of the gate itself, or the underlying gate oxide and/or channel regions. This outcome is a consequence of the fact that the third and deep implant is performed following gate definition.
Another disadvantage associated with conventional transistor fabrication is the potential for high leakage currents or junction shorts at the vertical interfaces between source/drain regions and adjacent isolation structures. Trench isolation structures are fabricated by etching a trench or moat in the substrate and refilling the trench with one or more insulating materials. The fill is then planarized to the substrate surface. Exact planarity is seldom achieved. Indeed, portions of the substrate may protrude above the isolation structure. Depending on the height of the protrusions, the later-formed silicide layer may wrap around the protrusion and form a conducting pathway to the underlying well. The result may be high leakage currents or even direct junction shorting.
A conventional method for treating the problem of poor planarity is the aforementioned performance of a supplementary deep source/drain implant. However, as noted above, this technique performed in the conventional manner is not without drawbacks.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a source/drain region in a substrate is provided that includes forming a stack on the substrate with a gate electrode and an insulating layer positioned on the gate electrode that has etch selectivity to the gate electrode. A first doped region is formed in the substrate adjacent to the stack with a first horizontal junction. A second doped region is formed in the substrate that overlaps the first doped region and has a second horizontal junction positioned beneath the first horizontal junction. An implant of impurity ions into the substrate is performed to establish a third doped region that overlaps the second doped region and has a third horizontal junction positioned beneath the second horizontal junction. The insulating layer substantially prevents impurity ions from penetrating through the gate electrode. The substrate is heated to activate the first, the second and the third doped regions.
In accordance with another aspect of the present invention, a method of fabricating a

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