Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-02
2001-04-24
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S514000, C438S533000, C438S565000, C438S637000, C438S783000
Reexamination Certificate
active
06221747
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit.
2. Description of Related Art
High-density integrated circuits, such as VLSI (Very Large Scale Integration) ICs, are typically formed with a multi-level interconnect structure including two or more levels of metallization layers for electrically interconnecting the various components in the integrated circuits. A multi-level interconnect structure includes a base layer of met-allization layer which is electrically connected to the source/drain regions of the MOS transistors formed in the integrated circuit, and at least a second layer of metallization layer which is separated from the base layer of metallization layer by an insulating layer, with the second layer of metallization layer being electrically connected to the base layer of metallization layer via a conductive plug formed in the insulating layer. Still another or more layers of metallization layers can be formed over the second layer of metallization layer to constitute the multi-level interconnect structure.
It is to be noted that, in the literature of IC fabrication, the term “contact plug” customarily refers to a conductive plug that is interconnected between an upper level of metallization layer and a conductive part in the substrate, such as a source/drain region of a MOS transistor, whereas the term “via plug” refers to a conductive plug that is interconnected between an upper level of metallization layer and a lower level of metallization layer. In this specification, the two terms “contact plug” and “via plug” are collectively referred to as “conductive plug”.
One drawback to the conventional method for fabricating a conductive plug, however, is that undesired insulative materials exist at the junction between the plug and its connected part, thus resulting in a high junction resistance that causes a high resistance-capacitance (RC) time delay to the signal being transmitted through the plug. This degrades the performance of the resulting IC device.
A conventional method for fabricating a contact plug comprises forming an insulating layer on a provided substrate, performing a photolithography and etching process to form an opening within a insulating layer exposing a part of the substrate, and forming a doped polysilicon layer as a plug in the opening.
One drawback to the foregoing process, however, is that the resistance of the junction between the resulting plug and the substrate undesirably high due to two reasons. First, after the etching process used to form the opening, a small amount of the reactant used in the etching process is left at the bottom of the resulting opening and these remnants are considerably high in electrical resistance. Second, a thin oxide layer grows on the exposed surface of the substrate due to exposure to oxygen through the opening and the oxide layer is also considerably high in electrical resistance. These unwanted insulative materials undesirably increase the junction resistance of the resulting plug, thus causing an RC (resistance-capacitance) delay in the signal being transmitted through the plug. The performance of the resulting IC devices is therefore degraded.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a conductive plug with a low junction resistance in an integrated circuit. A semiconductor substrate is provided. The substrate has a conductive region therein, such as a source/drain region or a metallization layer. An insulating layer with an opening at a specified location therein is formed over the substrate. The opening in the insulating layer exposes the conductive region. A second insulating layer, such as a native oxide layer or a remaining insulating layer, is positioned on the conductive region within the opening. A doping process is performed to dope a selected dopant into the second insulating layer on the conductive region through the opening so as to convert the second insulating layer into a doped region. The resistance of the second insulating layer is thus decreased. A depositing process is performed to deposit polysilicon into the via opening and over the second insulating layer to form the intended plug, wherein the deposition process being performed at a high-temperature that can cause the dopant atoms in the doped region to diffuse.
The method of the invention is characterized by the inclusion in the doping process of formation of a doped region in the exposed area through the contact opening or via opening. In the conventional method, the exposed area would be formed with an undesired oxide layer or laid with undesired reactant remnants after the etching process for forming the contact opening or via opening. When subjected to high-temperature conditions during subsequent deposition process, the dopant atoms in the doped region would diffuse into these undesired insulative matters, thereby reducing the junction resistance of the resulting contact or via plug.
REFERENCES:
patent: 5470794 (1995-11-01), Anjum et al.
patent: 5620926 (1997-04-01), Itoh
patent: 5909048 (1999-06-01), Sugino
patent: 5998255 (1999-12-01), Kung et al.
patent: 6096391 (2000-08-01), Muffoletto et al.
Chen Kuen-Chu
Chen Weng-Yi
Wu Juei-kuo
Jr. Carl Whitehead
Oppenheimer Wolff & Donnelly LLP
Thomas Toniae M.
United Integrated Circuits Corp.
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