Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-04
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S393000, C438S396000, C438S655000, C438S682000, C438S683000, C438S239000, C438S970000
Reexamination Certificate
active
06204116
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88107842, filed May 14, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a capacitor with a low-resistance electrode structure in a mixed-mode IC device.
2. Description of Related Art
Since IC fabrication technology has advanced to the deep-submicron level, a single IC device can now provide a high packing density and functionality. However, the deep-submicron downsizing of the various semiconductor components in the IC device can also affect the performance of the IC device.
A mixed-mode IC device is a type of IC device that includes both analog and digital circuitry on the same device. It typically includes a capacitor element which can function as a switched capacitor filter for the analog circuitry and function as a storage node in the digital circuitry for data storage. The electrodes of the capacitor element are typically formed from doped polysilicon. One drawback to using doped polysilicon to form the capacitor electrodes, however, is that doped polysilicon has a high resistance that still causes the charge/discharge process to be unsatisfactorily slow. The resulting IC device thus has a low performance. Moreover, at the deep submicron level of integration, the electrode resistance is even further increased due to the downsizing of the electrodes, furtherdegrading the IC's performance.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new semiconductor fabrication method for fabricating a capacitor, which method can help reduce the resistance of the electrode structure of the capacitor.
In accordance with the foregoing and other objectives of this invention, a new IC fabrication method is provided for fabricating a capacitor with a low-resistance electrode in a mixed-mode IC device. The method of the invention is designed for fabricating a capacitor in a mixed-mode integrated circuit constructed on a semiconductor substrate having a first area where a gate and a pair of source/drain regions are defined and a second area where a first electrode is defined. The method of the invention comprises the steps of: (1) forming a first dielectric layer covering the first electrode; (2) forming a doped polysilicon layer over the first dielectric layer, (3) forming a metal silicide layer over the doped polysilicon layer; (4) forming a second dielectric layer over the metal silicide layer; and (5) performing a selective removal process on the second dielectric layer, the metal silicide layer, and the doped polysilicon layer, with the remaining parts thereof in combination constituting a second electrode, and the second electrode, the first dielectric layer, and the first electrode in combination constituting the intended capacitor.
The method of the invention is characterized by the incorporation of a metal silicide layer in the second electrode, which can significantly help reduce the overall resistance of the second electrode, thereby allowing the resulting capacitor to charge/discharge more rapidly, thus allowing an increase in the overall performance of the resulting mixed-mode IC device. Moreover, by the method of the invention, since the second dielectric layer and the first dielectric layer are identical in material and thickness, it is easy to distinguish them as etching end points, allowing the etching process to be less complex and thus easier to perform than the prior art.
REFERENCES:
patent: 4411734 (1983-10-01), Maa
patent: 5356826 (1994-10-01), Natsume
patent: 5597759 (1997-01-01), Yoshimori
patent: 5882946 (1999-03-01), Otani
patent: 6114199 (2000-09-01), Isobe et al.
Wolf et al., “Silicon Processing for the VLSI Era vol. 2- Process Integration,” pp. 201-204, 1990.
Huang Jiawei
J.C. Patents
Kennedy Jennifer M.
Niebling John F.
Worldwide Semiconductor Manufacturing Corp.
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