Method of fabricating a capacitor under bit line structure...

Details Method of fabricating a capacitor under bit line structure... Method of fabricating a capacitor under bit line structure...

2001-02-15

2001-10-09

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000

Reexamination Certificate

active

06300191

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of fabricating a capacitor under bit line (CUB), structure, for a dynamic random access memory (DRAM, device.
(2) Description of Prior Art
The continuing increase in the density of DRAM cells, achieved via micro-miniaturization, or the ability to fabricate devices with sub-micron features, has led to difficulties in achieving the desired capacitance for an individual DRAM device. The horizontal dimensions of a stacked capacitor structure, used in each DRAM device, in now limited by the decreasing size, or width, of the DRAM device, thus placing greater demands on increasing the height, or vertical dimension of the stacked capacitor structure, to provide the needed surface area and thus the needed capacitance. However increasing the vertical dimensions of the DRAM, stacked capacitor structure, results in the use of thicker insulator layers, used to accommodate deeper capacitor openings, and to provide adequate passivation for the underlying stacked capacitor structure. The use of thicker insulator layers in turn, result in added process complexity in terms of an increased aspect ratio for the dry etched, narrow diameter bit line contact holes, used in the CUB DRAM designs. In addition the decreased spacing between the stacked capacitor structure and the bit line structure, can lead to electrical leakage or shorts between these key DRAM elements.
This invention will describe a novel method of fabricating a CUB DRAM device, in which the aspect ratio of the dry etched, bit line contact hole is not increased as a result of increasing vertical dimensions of the capacitor structure. In addition this invention will teach a method of providing insurance against leakage, or shorts, that can occur between the bit line contact structure and the capacitor structure. Prior art, such as Tseng, in U.S. Pat. No. 5,926,710, presents a fabrication procedure for a stacked capacitor structure, while Jost et al, in U.S. Pat. No. 6,110,774, show a fabrication procedure for a capacitor under bit line capacitor structure. However these prior arts do not use the novel process steps and process sequences, presented in the present invention, which allow a reduction in bit line contact hole aspect ratio, and improved isolation between the bit line and capacitor structures, to be realized.
SUMMARY OF THE INVENTION
It is an object of this invention to form a capacitor under bit line (CUB), DRAM device, featuring a reduction of the aspect ratio of a bit line contact hole, and featuring improved isolation between the stacked capacitor structure and the bit line structure.
It is another object of this invention to reduce the process complexity of forming a bit line contact structure in a narrow diameter contact hole via forming the bit line contact plug structure, simultaneously with the formation of the capacitor storage node structure.
It is still another object of this invention to reduce leakage and shorts between the stacked capacitor, and bit line structures, via formation of insulator spacers on the sides of the bit line opening.
In accordance with the present invention a method of fabricating a CUB DRAM device, featuring process steps and sequences which reduce the aspect ratio of a bit line contact hole, and reduce the risk of leakage and shorts between a stacked capacitor structure and a bit line structure, is described. After formation of transfer gate transistors, and deposition of a first insulator layer, self-aligned contact (SAC), openings are formed in the first insulator layer, exposing source/drain regions of the transfer gate transistors. Formation of polysilicon plugs, in the SAC openings, are next made, with a first group of polysilicon plugs designed for storage node contact plugs, and with a second polysilicon plug to be used for a lower level, bit line contact plug. Deposition of a second insulator layer is followed by creation of capacitor openings in the second insulator layer, exposing the top surface of the storage node contact plugs, and simultaneous creation of a narrow diameter, bit line contact hole in the second insulator layer, exposing a portion of the lower level bit line contact plug. Deposition of a polysilicon layer coats the exposed surfaces of the capacitor openings, while completely filling the narrow diameter, bit line contact hole. After formation of a hemispherical grain silicon layer, on the underlying polysilicon layer, a chemical mechanical polishing procedure is used to simultaneous define the storage node structures, in the capacitor openings, as well defining an upper level, bit line contact plug in the narrow diameter, bit line contact hole. Deposition of a capacitor dielectric layer, a polysilicon layer, and a third insulator layer, are followed by a patterning procedure performed in the third insulator layer and in the polysilicon layer, resulting in definition of crown shaped capacitor structures, comprised of an underlying storage node structure, a capacitor dielectric layer, and an overlying top electrode structure, comprised from the polysilicon layer, and resulting in the simultaneous definition of a bit line opening in the third insulator layer, exposing the top surface of the upper level, bit line contact plug. After formation of insulator spacers, on the sides of the bit line opening, a bit line structure is formed in the bit line opening, overlying and contacting, the upper level, bit line contact plug.


REFERENCES:
patent: 5206183 (1993-04-01), Dennison
patent: 5874335 (1999-02-01), Jeng
patent: 5926710 (1999-07-01), Tseng
patent: 5933726 (1999-08-01), Nishimura et al.
patent: 6037213 (2000-03-01), Shih et al.
patent: 6083789 (2000-07-01), Huang et al.
patent: 6110774 (2000-08-01), Jost et al.

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