Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-19
2001-09-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S241000, C438S253000, C438S254000, C438S396000, C438S397000, C438S398000, C438S964000
Reexamination Certificate
active
06294426
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a capacitor under bit line (CUB), dynamic random access memory (DRAM), device.
(2) Description of Prior Art
As the density of DRAM cells increase, the dimensions of the DRAM device has to be decreased. The decreasing size of a specific DRAM device adversely influences the ability to provide the needed DRAM capacitance. Increasing the vertical dimensions for DRAM, crown shaped capacitor structures have allowed the desired capacitance values for DRAM devices to be achieved. The increase in these vertical dimensions is usually accomplished via formation of the crown shaped capacitor structure, located in capacitor openings, and in turn formed in thick insulator layers. However the use of thick insulator layer for the capacitor openings, result in high aspect ratio for bit line contact holes, used in for capacitor over bit line (CUB), designs. The additional thickness of insulator, needed to increase the vertical dimension of the crown shaped capacitor structure, results in difficulties when anisotropically dry etching a narrow diameter, deep, opening, to expose a bit line region.
This invention will describe a novel process sequence in which the desired increase in the vertical dimensions of the crown shaped capacitor structure is achieved via formation of the capacitor openings in thicker insulator layers, however without increasing the aspect ratio for the dry etched, narrow diameter bit line contact hole. Prior art, such as Tu et al, in U.S. Pat. No. 6,100,129, as well as Chen et al, in U.S. Pat. No. 6,077,742, describe methods of fabricating DRAM crown shaped capacitor structures. These prior arts however do not describe the novel process sequence of this present invention, where a CUB DRAM device is fabricated with increased capacitance, as a result of increased vertical, crown shaped features, without increasing the aspect ratio of the bit line contact hole opening.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a capacitor under bit line (CUB), structure for a DRAM device.
It is another object of this invention to increase DRAM capacitance via removal of a top portion of a polysilicon plug, exposed at the bottom of a capacitor opening in a composite insulator layer, increasing the depth of a capacitor opening, thus allowing a subsequent crown shaped capacitor structure, with increased capacitance resulting from increased vertical dimensions, to be formed, overlying and contacting the shortened polysilicon plug located in the capacitor opening.
It is still another object of this invention to prevent removal of a top portion of a polysilicon plug used for contact to an overlying bit line structure, thus not increasing the aspect ratio for a anisotropic dry etched, bit line contact hole opening, used to expose the top surface of the non-shortened polysilicon plug.
In accordance with the present invention a method of forming a CUB DRAM device, featuring increased capacitance, resulting from increasing the depth of a capacitor opening in a composite insulator layer, without however increasing the aspect ratio for a bit line contact hole, formed in the same composite insulator layer, is described. After formation of transfer gate transistors, and deposition of a first insulator layer, self-aligned contact (SAC), openings are formed in the first insulator layer, exposing source/drain regions of the transfer gate transistors. After formation of polysilicon plugs, in the SAC openings, a composite insulator layer, comprised of a thick silicon oxide layer, and a thin overlying silicon nitride layer, is deposited. Openings are made in the composite insulator layer, and in a top portion of the first insulator layer, exposing top portions of a first group of polysilicon plugs to be used for contact to a subsequent, overlying capacitor structure, while the same composite insulator layer, located in a region overlying a second polysilicon plug, to be used for contact to a subsequent bit line structure, remains unremoved. Selective removal of the exposed portions of the first group of polysilicon plugs, result in a capacitor opening formed in both the composite insulator layer, and in a top portion of the first insulator layer, exposing the top surface of the first group of polysilicon plugs, now embedded only between the gate structures of the transfer gate transistors. Crown shaped capacitor structures, comprised of: an underlying bottom electrode structure, featuring hemispherical grain silicon; a capacitor dielectric layer; and an overlying top electrode structure; are next formed in the capacitor opening, overlying and contacting the truncated first group of polysilicon plugs. After deposition of a second insulator layer, a bit line contact hole is opened in the second insulator layer, and in the composite insulator layer, exposing the top surface of the non-truncated, second polysilicon plug.
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Tu Kuo-Chi
Yu Chih-Hsing
Ackerman Stephen B.
Kennedy Jennifer M.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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