Method of fabricating a capacitor electrode structure in a dynam

Details Method of fabricating a capacitor electrode structure in a dynam Method of fabricating a capacitor electrode structure in a dynam

1999-02-16

2000-03-14

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

060372176

ABSTRACT:
An integrated circuit (IC) fabrication method is provided for the fabrication of an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device. In this method, damascene technology is used, which can help reduce the height difference between the memory cell region and the peripheral region, thus eliminating the required planarization process in the prior art. Moreover, this method can provide an electrode structure having a large surface area that allows the associated capacitor to be considerably increased in capacitance as compared to the prior art while requiring no increase in the layout area in the integrated circuit.

REFERENCES:
patent: 5874335 (1999-02-01), Jenq
patent: 5918122 (1999-06-01), Parekh et al.

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