Method of fabricating a buried bit line

Details Method of fabricating a buried bit line Method of fabricating a buried bit line

1998-07-10

1999-03-16

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438282, 438289, 438524, H01L 218236

Patent

active

058829725

ABSTRACT:
A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer. A portion of the second conductive layer is then removed and the remaining second conductive layer fills the trench wherein the remaining second conductive layer is electrically coupled with the first conductive layer and the shallow junction region.

REFERENCES:
patent: 4200968 (1980-05-01), Schroeder
patent: 4604150 (1986-08-01), Lin
patent: 5180680 (1993-01-01), Yang
patent: 5460987 (1995-10-01), Wen et al.
patent: 5504025 (1996-04-01), Fong-Chun et al.
patent: 5529954 (1996-06-01), Iijima et al.
patent: 5602049 (1997-02-01), Wen et al.
patent: 5668031 (1997-09-01), Hsue et al.

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