Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-29
2002-02-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S618000, C438S636000
Reexamination Certificate
active
06348375
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a bit line structure in wiring structures and a fabrication method thereof.
2. Description of the Related Art
With an increase in the integration of semiconductor devices, a critical dimension decreases. Control of the uniformity of a critical dimension becomes more and more important, thus increasing use of an anti-reflectance coating (ARC) film in a photolithographic process for patterning a material film on a semiconductor substrate. The ARC film has been necessarily adopted in a process for patterning a conductive film which is used as a wiring structure such as a bit line, etc.
The ARC film is formed on a material film to be patterned and suppresses diffused reflection on the surface of the material film. Since the diffused reflection on the surface of the material film is suppressed, accuracy by the photolithography can increase. Therefore, a more minute and uniform material film pattern can be attained.
The ARC film must be removed after the material film under the ARC film is patterned, i.e., after a bit line is formed, since the remaining ARC film can serve as an etching stopper in a subsequent process and thus cause an etch failure or a contact hole formation failure.
FIG. 1
is a cross-sectional view showing a conventional bit line structure for a semiconductor device. Referring to
FIG. 1
, a bit line
60
is formed on a first dielectric layer
23
. Here, the bit line
60
is comprised of conductive films, e.g., an impurity-doped polycrystalline silicon layer
61
and a tungsten silicide layer
63
.
A process for forming the bit line
60
is performed as follows. First, a direct contact hole and/or a direct contact pad can be formed by patterning the first dielectric layer
23
using a photolithographic process for interposing an ARC film on it. After removing the ARC film, a conductive film used as the bit line
60
is formed on the first dielectric layer
23
.
A second dielectric layer
25
covering the bit line
60
is formed after the bit line
60
is formed. The second dielectric layer
25
is patterned to form a buried contact hole
29
for exposing a semiconductor substrate
10
. The buried contact bole
29
is cleaned, and another conductive layer for filling the contact hole
29
, e.g., a storage node of a capacitor, is then formed. A conductive buried contact pad
31
can also be formed below the buried contact hole
29
.
Here, the bit line
60
may be damaged or oxidized by a subsequent process such as a storage node cleaning or forming process. Therefore, a spacer
27
for covering the sidewall of the buried contact hole
29
is introduced to prevent damage to or oxidation of the bit line
60
.
However, introduction of the spacer
27
on the sidewalls of the buried contact hole
29
substantially reduces the bottom critical dimension of the buried contact hole
29
, which may cause a reduction in a process margin in a subsequent process such as a process for forming a conductive film for filling the buried contact hole
29
. Also, the contact area, i.e., the interface, between the conductive film for filling the buried contact hole
29
and the lower buried contact pad
31
becomes substantially small, and thus a contact resistance can be increased.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a bit line structure for semiconductor devices, by which a buried contact hole can be formed while oxidation of a bit line is prevented, and an increase in contact resistance can be curbed since a more bottom critical dimension of the buried contact hole can be attained.
It is another object of the present invention to provide a method of fabricating a bit line structure for semiconductor devices, by which a buried contact hole can be formed while oxidation of a bit line is prevented, and an increase in contact resistance can be curbed since a more bottom critical dimension of the buried contact hole can be attained.
Accordingly, to achieve the first object, there is provided a bit line structure for semiconductor devices, comprising: a first dielectric film pattern formed on a semiconductor substrate and having a first contact hole exposing a part of the semiconductor substrate; a first conductive film pattern formed on the first dielectric film pattern, filling the first contact hole, and used as a bit line; a lower protecting layer pattern which protects the lower surface of the first conductive layer pattern on the interface between the first conductive layer pattern and the first dielectric layer pattern, and is comprised of an anti-reflectance coating (ARC) layer; a spacer on the sidewall of the first conductive film pattern; an upper protecting layer pattern which covers and protects the upper surface of the first conductive layer pattern and is comprised of an ARC layer; and a second dielectric layer pattern which insulates the first conductive film pattern, is isolated from the first conductive film pattern, and has a second contact hole for exposing the semiconductor substrate.
The spacer is formed of a nitride material selected from the group consisting of silicon nitride and silicon oxynitride. The lower protecting film pattern is a nitride-based ARC layer. The upper protecting film pattern is a nitride-based ARC layer. A second conductive film pattern for filling the second contact hole is further formed on the second dielectric film pattern.
To achieve the second object, there is provided a method of fabricating a bit line structure for semiconductor devices. In this method, a first dielectric layer is formed on a semiconductor substrate. A lower ARC layer is formed on the first dielectric layer to prevent diffused reflection on the surface of the first dielectric layer. A first dielectric layer pattern having a first contact hole exposing the semiconductor substrate is formed by patterning the lower ARC layer and the first dielectric layer. A first conductive layer for filling the first contact hole is formed on the lower ARC layer. An upper ARC layer for preventing diffused reflection on the surface of the first conductive layer is formed on the first conductive layer.
A first conductive layer pattern used as a bit line is formed by sequentially patterning the upper ARC layer, the first conductive layer, and the lower ARC layer. Also, upper and lower protecting film patterns are formed, which are respectively comprised of the upper and lower ARC layers and protect the first conductive layer pattern. Here, the upper and lower protecting film patterns are nitride-based ARC layers.
A spacer is formed on the sidewall of the first conductive layer pattern. The spacer is formed of a nitride material selected from the group consisting of silicon nitride and silicon oxynitride. A second dielectric layer pattern is formed, which covers the first conductive layer pattern, is isolated from the first conductive layer pattern, and has a second contact hole for exposing the semiconductor substrate.
After the step of forming the second dielectric layer pattern, a second conductive layer pattern for filling the second contact hole is further formed on the second dielectric film pattern.
According to the present invention, oxidation of a bit line is prevented, and a second contact hole, e.g., a buried contact hole, can be formed. Also, an additional spacer on the sidewalls of the buried contact hole can be excluded, thus a larger bottom critical dimension can be secured. Therefore, an increase in the contact resistance of a second conductive film pattern filling the buried contact hole can be prevented. Furthermore, a spacer formation process can be omitted, to simplify the bit line structure fabrication process.
REFERENCES:
patent: 5869901 (1999-02-01), Kusuyama
patent: 6074905 (2000-06-01), Hu et al.
patent: 6218292 (2001-04-01), Foote
patent: 10079430 (1998-03-01), None
Jeong Sang-sup
Lee Won-seok
Shin Kyoung-sub
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