Method of evaluating fault coverage

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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Details

714738, 714741, G01R 3128

Patent

active

061516945

ABSTRACT:
There is provided a method of evaluating fault coverage, which enables the complete implement action of the test of macro-blocks embedded in a LSI by performing fault simulation. According to the present invention, the fault simulation of a macro-block such as a CPU core is performed on the assumption that the fault simulation of 100% assumed faults or sufficient % assumed faults for practical purpose is performed on a reference chip with use of a standard test pattern. In the fault simulation process, the fault sampling is performed at first in the macro-block, and the fault simulation is performed by inputting the standard test pattern into the macro-block. Subsequently, the sampled faults are embedded in a newly developed chip having the same macro-block, and then the fault simulation for the newly developed chip is then performed again with use of a test pattern obtained by modifying the standard test pattern. A list of detected and undetected faults of the newly developed chip is compared with a list of detected and undetected faults of the reference chip detected by using the standard test pattern. When these lists are identical, it is assured that the test of the macro-block in the newly developed chip was properly performed by using the test pattern and that the satisfactory fault coverage was obtained.

REFERENCES:
patent: 4769817 (1988-09-01), Krohn et al.
patent: 5862149 (1999-01-01), Carpenter et al.
patent: 5991907 (1999-11-01), Stroud et al.
patent: 6061818 (2000-05-01), Touba et al.

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