Method of evaluating a semiconductor wafer

Details Method of evaluating a semiconductor wafer Method of evaluating a semiconductor wafer

1998-01-27

1999-04-27

Picardat, Kevin M.

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 14, G01R 3126, H01L 2166

Patent

active

058973273

ABSTRACT:
A MOS capacitor in which an insulating layer of thermal oxide film is disposed between the electrode 2 and the silicon wafer 1 is formed. While a light beam of an energy larger than 1.1 eV is irradiated on the electrode 2 and its periphery, electrons inject from the electrode 2 side (voltage is applied from the silicon wafer 1 side). The injected electrons are activated by the light irradiation. For both p-type or n-type semiconductor, the dielectric breakdown electric field strength can be precisely measured according to the degree of processing defects. The evaluation method is particularly effective for the n-type semiconductor wafer, which was difficult to evaluate by the prior art.

REFERENCES:
patent: 5391502 (1995-02-01), Wei
patent: 5396169 (1995-03-01), Buehler et al.
patent: 5543334 (1996-08-01), Yoshii et al.
patent: 5635410 (1997-06-01), Kusudo
patent: 5668062 (1997-09-01), Hyun et al.

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