Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-21
2003-03-11
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S585000, C438S706000, C438S734000
Reexamination Certificate
active
06531349
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, more in detail to the method for fabricating the semiconductor device suitably used for formation of a gate electrode of MOSFET.
(b) Description of the Related Art
With higher integration of a semiconductor device, a technology is developed in which the dimensions of the gate electrode of the MOSFET are reduced to have a narrower width thereof than a minimum width of a conventional gate electrode formed by the photolithographic technology currently utilizable. In the developed technology, the gate electrode is formed by patterning, by using the photolithography and dry-etching, of a polycrystalline silicon film deposited on a gate insulation film. After the polycrystalline silicon film is etched until the thickness thereof is reduced to a specified thickness in a main etching process in which a selective ratio between the polycrystalline silicon film and the gate oxide film (SiO
2
) is low, the etching is continued to the surface of the gate oxide film in an over etching process in which the selective ratio is higher.
However, when the gate electrode is formed in accordance with the above technology by using the dry etching, problems such as the irregularity of the pattern size, and the in-plane difference in shape, arise due to the difference of the pattern density on the wafer.
JP-A-11(1999)-260799 describes a method of processing a finely-deposited thin layer for overcoming the above problem. The method will be described referring to FIG.
1
.
As shown therein, an oxide film (SiO
2
film)
302
having a thickness of 3 nm, a doped polycrystalline silicon (DOPOS) film
303
having a thickness of 200 nm
303
, and a silicon nitride film
304
are sequentially deposited on a silicon substrate
301
. The silicon nitride film
304
is photolithographically formed, and has the minimum width of 0.13 &mgr;m.
The DOPOS film
303
is etched in a plurality of steps by using the silicon nitride film
304
as a mask. In a first step, a native oxide film generated on the DOPOS film is removed by means of etching for 5 seconds under the conditions that chlorine gas is provided at a flow rate of 120 ml/min under an ambient pressure of 0.1 Pa, an RF electric power of 160 mW and a microwave power of 500 mW. In a second step or a main etching step, the etching of the DOPOS film
303
is conducted at a lower selective ratio between the DOPOS film
303
and the oxide film
302
at a chlorine flow rate of 108 ml/min and an oxygen flow rate of 12 ml/min.
The remaining thickness of the DOPOS film
303
during the main etching step is measured by using an optical interference real time monitor for film thickness, and the second step is finished and a third step or an over-etching step starts when the film thickness reaches to 30 nm. In the over-etching step, in order to increase the selective ratio between the DOPOS film
303
and the oxide film
302
, an oxygen flow rate and a HBr flow rate are established to be 3 ml/min and 100 ml/min., respectively.
The combination of the main etching step having the lower selective ratio between the DOPOS film
303
and the oxide film
302
and the over etching step having the higher selective ratio for the etching of the DOPOS film
303
prevents the occurrence of etching damage in the gate oxide film
302
. Especially, the measurement of the film thickness with the optical interference real time monitor controls the conversion from the main etching step to the over etching step in accordance with the remaining DOPOS film thickness.
However, in the method for forming the finely-deposited thin layer described in the above publication, an undesired sub-trench is formed in the DOPOS film due to the difference of the pattern densities on the wafer, thereby generating the difference in the film thickness of the remaining DOPOS film.
As shown in
FIG. 2A
, the small sub-trench
305
is generated on the sidewall portions of the DOPOS film
303
especially in an area where a pattern density is large during the main etching. As shown in
FIG. 2B
, the sub-trench
305
proceeds toward the surface of the gate oxide film
302
at the time of the completion of the main etching, and thereafter, proceeds toward the surface of the substrate
301
in the succeeding over etching step, thereby generating damages on the substrate surface as shown in
FIG. 2C
, that is, deteriorating the characteristics of the MOSFET.
The reasons of generating the sub-trench include the increase of the ion density at the periphery of the gate electrode due to the reflection of the ions on the sidewalls of the photoresist and the nitride film, and especially the electron shading may provide an influence to the incident orbits of the ions in the region where the pattern density is high. The generation of the sub-trenches is affected by a deposition seed, and an amount thereof or the degree of covering the film. As a result, the irregularity of the remaining DOPOS film is largely influenced thereby. However, an effective means for suppressing the irregularity is not conventionally proposed.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a method for fabricating a semiconductor device, especially the method for patterning a gate electrode of MOSFET in which damage due to etching of a substrate and a gate oxide film is hardly generated in the fabrication of the semiconductor device.
Thus, the present invention provides a method for fabricating a semiconductor device including the steps of: sequentially forming an oxide film and a polycrystalline silicon film overlying a substrate; and selectively dry-etching the polycrystalline silicon film in consecutive two processes including a main etching process for dry-etching the polycrystalline silicon film under existence of Cl
2
, HBr and CF
4
and an over-etching process for dry-etching the polycrystalline silicon film under existence of HBr and oxygen.
In accordance with the present invention, the gate electrode film is etched in the main etching process with the excellent dimension controllability and is etched in the over etching process with the higher selective ratio between the gate electrode film and the gate oxide film. In the main etching process, the halogen-containing gas such as CF
4
is deposited in the sub-trenches formed during the process. Accordingly, the sub-trenches in the polycrystalline silicon film are diminished to make uniform the thickness of the polycrystalline silicon film after the main etching process. The uniform film thickness prevents the damages liable to occur in the oxide film and on the substrate surface in the succeeding over etching process.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 5259923 (1993-11-01), Hori, et al.
patent: 6069091 (2000-05-01), Chang et al.
patent: 6194284 (2001-02-01), Chen
patent: 04-096223 (1992-03-01), None
patent: 06-283477 (1994-10-01), None
patent: 08-306672 (1996-11-01), None
patent: 11-260799 (1999-09-01), None
patent: 357411 (1999-05-01), None
Ikezawa Nobuyuki
Yoshida Kazuyoshi
Chaudhuri Olik
Chen Jack
Katten Muchin Zavis Roseman
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