Method of etching a substrate

Details Method of etching a substrate Method of etching a substrate

1999-06-30

2001-09-11

Mills, Gregory (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S724000, C438S714000, C438S743000, C438S744000

Reexamination Certificate

active

06287978

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor manufacturing, and more particularly to a process for selectively etching a silicon dioxide layer disposed on a silicon nitride layer, useful when etching features have submicron geometries.
BACKGROUND OF THE INVENTION
With geometries shrinking, it is becoming more difficult to align small contacts in between closely spaced wordlines or other conductive structures. Therefore, an etch is needed which would etch an oxide layer and stop on the underlying nitride layer. The highly selective etch should also display consistency for manufacturing purposes.
Current manufacturing processes of multilayer structures typically involve patterned etching of areas of the semiconductor surface which are not covered by a pattern of protective photoresist material. These etching techniques use liquid or wet etching materials, or dry etching with halogens or halogen-containing compounds.
Etching of the multilayer structures can also be conducted in a gas phase using known techniques, such as plasma etching, ion beam etching, and reactive ion etching. The use of gas plasma technology provides substantially anisotropic etching using gaseous ions, typically generated by a radio frequency (RF) discharge.
In gas plasma etching the requisite portion of the surface to be etched is removed by a chemical reaction between the gaseous ions and the subject surface. In the anisotropic process, etching takes place primarily in the vertical direction so that feature widths substantially match the photoresist pattern widths. Anisotropic etching is utilized when feature sizing after etching must be maintained within specific limits so as not to violate alignment tolerances or design rules.
Higher density multilayer structures such as 64 and 256 Megabit DRAM require an additional amount of alignment tolerance which can not be addressed by current photolithographic means. In such applications, an etch stop technology could be used to supply the desired tolerance.
In an etch “stop” system, an etch “stop” layer is deposited on underlying structures. The superjacent layer is disposed over the underlying etch “stop” layer through which the desired patterns will be defined. The etch “stop” layer will then be used to terminate the etch process once the superjacent layer has been completely removed in the desired pattern locations. Thus, the etch “stop” layer acts to protect structures underlying the etch “stop” layer from damage due to the dry chemical etch of the superjacent layer.
The preferred etch “stop” material is silicon nitride because its properties are well known, and it is currently used for semiconductor fabrication. The preferred superjacent layer is silicon dioxide, or other oxide such as, BPSG.
The etch stop process must have three basic properties, namely, (1) a high etch rate for the superjacent layer which (2) produces substantially vertical sidewalls, and (3) has a high selectivity of the superjacent layer being etched down to the etch “stop” layer.
A problem of profile control occurs with respect to etching of a multilayer structure having a silicon dioxide layer disposed on an underlying silicon nitride layer. Profile control using pure chemical etching (e.g., using hydrofluoric acid) tends to produce structures that do not have vertical sidewalls.
Dry etch processing usually produces a more vertical profile because of the ion bombardment aspect of the process. However, the dry etch process can produce a contact wall that slopes out from the bottom, rather than at an angle of 90°, if the wrong mix of process parameters are used. These parameters can include, but are not limited to; fluorocarbon, RF power, and pressure.
The same ion bombardment aspect of the dry etch process used to produce straight sidewalls has a very negative effect on oxide to nitride selectivity. High energy ions needed to etch both oxide and nitride do so by disassociating a chemical bond at the oxide and/or nitride surface. However, the disassociation energy needed for nitride is less than that required for oxide.
Hence, CH
2
F
2
is added to offset the disassociation properties of nitride as compared to oxide. The CH
2
F
2
produces a polymer deposition on the nitride surface that acts to passivate the nitride surface and thereby reduce the dry etch removal rate. However, the silicon dioxide etch rate is sustained at a much higher rate than that of silicon nitride.
Current etch process technology for etching an SiO
2
layer on an underlying Si
3
N
4
layer using a dry etcher, such-as an RIE or MRIE etcher, cannot produce SiO
2
to-Si
3
N
4
selectivities above 5-6:1 with adequate profile and SiO
2
etch rate characteristics.
Almost all of the current etch processes which involve high selective etches, rely on cooler temperatures to obtain those selectivities. See, for example, “Temperature Dependence of Silicon Nitride Etching by Atomic Fluorine,” and “Selective Etching of Silicon Nitride Using Remote Plasmas of CF
4
and SF
6
,” both by Lee M. Loewenstein. The latter reference uses an Arrhenius plot having a negative slope to illustrate that the nitride etch rate increases as a function of substrate temperature.
Therefore, a need exists for a process of etching a SiO
2
layer on an underlying Si
3
N
4
layer, at a high SiO
2
etch rate. Furthermore, there exists a need for an etch at a high selectivity of SiO
2
with respect to the underlying Si
3
N
4
, to form an etched multilayer structure at a controlled predetermined profile in which the resulting sidewalls are substantially normal to the substrate.
SUMMARY OF THE INVENTION
The present invention provides unexpected and very key improvements over the current etch processes. The present invention teaches away from current thought, by using increased temperatures to achieve increased selectivity. In addition to improved selectivity, the higher temperatures help reduce the polymer build-up inside the chamber.
The process of the present invention meets the above-described existing needs by forming an etched multilayer structure, in which the sidewalls of the SiO
2
layer are substantially normal to the substrate, at a high SiO
2
etch rate, and at a high selectivity of SiO
2
with respect to the underlying Si
3
N
4
. This is accomplished by heating various portions of the etch chamber while employing a process for etching the SiO
2
layer down to the Si
3
N
4
stop layer.


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