Method of enlarging contact area of a gate electrode,...

Details Method of enlarging contact area of a gate electrode,... Method of enlarging contact area of a gate electrode,...

2006-03-28

2006-03-28

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S267000, C438S306000, C257S335000

Reexamination Certificate

active

07018914

ABSTRACT:
A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same.

REFERENCES:
patent: 6169017 (2001-01-01), Lee
patent: 2000-36594 (2000-02-01), None

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