Method of enhancing electrostatic discharge (ESD) protection cap

Details Method of enhancing electrostatic discharge (ESD) protection cap Method of enhancing electrostatic discharge (ESD) protection cap

1996-05-20

1999-06-29

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, H01L 218246

Patent

active

059181273

ABSTRACT:
A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor. The breakdown voltage controlling areas are heavily doped, thereby reducing the breakdown voltage at the junction between the drain and the p-well in the n-type CMOS transistor. This enhances the ESD protection capability of the integrated circuit.

REFERENCES:
patent: 4904615 (1990-02-01), Okuyama et al.
patent: 5221635 (1993-06-01), Duvvury
patent: 5374565 (1994-12-01), Hsue et al.
patent: 5413949 (1995-05-01), Hong
patent: 5545772 (1996-08-01), Lee et al.

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