Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-04-27
2003-02-04
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S585000, C438S514000, C438S766000, C438S770000
Reexamination Certificate
active
06514843
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device fabrication, and more particularly to a method for fabricating metal oxide semiconductor (MOS) transistors wherein the rate of corner oxidation is enhanced without significantly increasing the thermal budget of the overall processing scheme.
BACKGROUND OF THE INVENTION
Modem Si-based metal-insulator-semiconductor (MIS) field effect transistors (FETs) are fabricated with the use of so-called sidewall or corner oxidation of the gate corner. Sidewall oxidation processes are routinely employed in conventional process flows such as complementary metal oxide semiconductor (CMOS) logic, static random access memory (SRAM), dynamic random access memory (DRAM), embedded DRAM, flash memories and other like processing flows.
As is known to those skilled in the art, sidewall oxidation of the gate corners thickens the gate insulator at the gate corner. Thick corner insulators prevent electrical breakdown at the device corners. The corner insulator also reduces the electric field by effectively rounding the corner during oxidation. A higher corner electric field can produce large hot-carrier effects leading to poor transistor reliability. In addition, the planar oxide grown during corner oxidation is used as a screen oxide for a subsequent ion-implantation step, thus, simplifying process integration flow. All these benefits of sidewall (or corner) oxidation are well known in the art; therefore a detailed discussion concerning the same is not needed herein.
In prior art processes, oxidation of the gate corners is generally carried out relatively late in the process flow. For example, oxidation of the gate corners typically occurs after well and channel implantations have been performed with the gate stack already present on the substrate. Thermal budget of the corner oxidation is therefore a very important parameter that must be taken into account when fabricating transistor devices. High thermal budget at a late stage of the process flow can cause undesirable dopant diffusion; and reaction and intermixing of the gate stack, gate insulator and channel materials. It is, therefore, very desirable to reduce thermal budget of the corner oxidation without degrading corner oxide quality and reliability.
Corner oxidation is usually carried out in an oxidizing ambient such as O
2
, H
2
O or oxygen radicals. Wet (H
2
O) or free radical assisted oxidation processes are preferred due to their fast rates and thus low thermal budgets. However, introduction of new materials into the gate stack may hinder such a trend. Metal gates and high dielectric constant, k, gate insulators may not be compatible with fast rate oxidation processes. For example, water molecules and oxygen radicals can oxidize a gate metal during gate corner oxidation. A specific oxidizing ambient is needed to selectively oxidize Si, but not the metal. It is well known in the art that such mixtures for selective corner oxidation are low-rate oxidation ambients. Due to various compatibility requirements on the corner oxidation ambient, it is highly desirable to reduce thermal budget of the corner oxidation independently of the oxidation ambient.
In view of the above-mentioned drawbacks with prior art corner oxidation processes, there is a continued need for developing a new and improved corner oxidation method that enhances the rate of corner oxidation without significantly increasing the thermal budget of the overall process flow.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method for enhancing the oxidation of transistor gate corners.
A further object of the present invention is to provide a method for enhancing gate corner oxidation which does not significantly increase the thermal budget of the overall processing flow.
A yet further object of the present invention is to provide a method for enhancing gate corner oxidation that is independent of the oxidation ambient employed.
An even further object of the present invention is to provide a method for enhancing gate corner oxidation using processing steps that are compatible with a variety of gate stack structures including various implementation of metal gates and high-k gate insulators. Note that the term “high-k” is used herein to denote a dielectric material that has a dielectric constant (measured in terms of a vacuum) that is greater than SiO
2
.
These and other objects and advantages are achieved by implanting non-oxidation retarding or Si ions into the transistor gate corners and thereafter exposing the implanted gate corners to an oxidizing ambient. The transistors employed in the present invention include, but are not limited to: MIS, MOSFET and other like transistors which include gate corners.
Specifically, the method of the present invention comprises the steps of:
(a) implanting ions into gate corners of a Si-containing transistor, wherein said ions are selected from non-oxidation retarding ions, Si ions and mixtures thereof; and
(b) exposing the Si-containing transistor including the implanted gate corners to an oxidizing ambient.
The phrase “non-oxidation retarding ions” is used herein to denote ions that do not lower the rate of oxidation of silicon. Illustrative examples of such non-retarding oxidation ions include, but are not limited: O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, Xe and mixtures thereof including mixtures with Si ions.
As stated above, the transistor employed in the present invention is a Si-containing transistor. The phrase “Si-containing transistor” as used herein denotes a transistor wherein at least one of the following regions: substrate, gate dielectric, gate conductor or any combination thereof, comprises a Si-containing material.
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patent: 5869385 (1999-02-01), Tang et al.
patent: 5920782 (1999-07-01), Shih et al.
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Dokumaci Omer
Gluschenkov Oleg
Hegde Suryanarayan G.
Kaplan Richard
Khare Mukesh
Guerrero Maria
Jr. Carl Whitehead
Scully Scott Murphy & Presser
Underweiser, Esq. Marian
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