Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-04-13
2004-03-16
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C438S118000
Reexamination Certificate
active
06707163
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit packaging and, more specifically, to integrated circuit packages utilizing preformed adhesive layers for affixing package components to each other.
BACKGROUND OF THE INVENTION
Solder ball grid array (BGA) integrated circuit packages are employed to encapsulate integrated circuit die for mounting on printed circuit boards (PCBs) within various electronic devices such as telecommunications equipment. During mounting, electrical connection to packaged integrated circuits is achieved by reflowing the solder balls while in contact with corresponding connection traces on the printed circuit board onto which the package is being mounted. Optional thin mounting profiles, high package “pin” counts, and ease of mounting are features which make ball grid array packages attractive for a variety of applications including general purpose processors, digital signal processors (DSPs), and the like.
For “dense” integrated circuits having large numbers of closely spaced, small feature size devices, a metallic heat spreader is often utilized within ball grid array packages to dissipate heat generated during operation of the integrated circuit. As illustrated by the exploded view shown in
FIG. 4
, a ball grid array package
400
of the type described typically includes a printed circuit board substrate
401
having a cavity
402
therein, which is affixed to a metal heat spreader
403
utilizing a preformed adhesive layer
404
having a hole corresponding is size and position with cavity
402
. The integrated circuit die (not shown) is mounted within the cavity, affixed to heat spreader
403
, with wire bonds (not shown) connecting bonds pads in the integrated circuit die to bonding sites on the substrate
401
.
A significant defect commonly found with packages of the type shown is the presence of voids between the surfaces of adhesive layer
404
and the surfaces of the components (substrate
401
and heat spreader
403
in this case) being joined by adhesive layer
404
. As the components are being affixed utilizing adhesive layer
404
, air is often randomly entrapped between the surfaces of the components and the surfaces of adhesive layer
404
. If not removed before the adhesive layer
404
hardens, uncontrolled voids (pockets of trapped air) will be formed in the finished package between the adhesive layer
404
and adjoining components. Such voids may be removed by high vacuum and high pressure environments commonly employed in production of printed wiring boards (PWBs), but requires heavy industrial equipment.
Two problems have been found to frequently arise during assembly and mounting of the package
400
as a result of uncontrolled voids in the adhesive layer
404
: die delamination and voids within the encapsulant for the package
400
. Die delamination is caused by the expansion of air entrapped between the adhesive layer and adjoining components, applying an internal pressure to cause separation of the package components from the adhesive layer
404
when the packaged device is heated during fabrication of the packaged device or subsequent mounting of the packaged device in a system.
Voids in the package encapsulant are similarly caused by gradual release of entrapped air while the encapsulant is being cured (typically at temperatures of approximately 175° C.). If these voids occur at the outer surface of the encapsulant, the packaged device is naturally rejected. On occasion, however, the air bubble does not reach the surface of the encapsulant and remains inside, a “buried” void which can result in damage to the die or to the bonding wires inside the encapsulant. In both case, encapsulant voids affect manufacturing yield and long term reliability of the product.
There is, therefore, a need in the art for improving integrated circuit packages utilizing preformed adhesive layers.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an integrated circuit package, a preformed adhesive layer for joining components within integrated circuit packaging which includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; and the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.
REFERENCES:
patent: 5391250 (1995-02-01), Cheney et al.
patent: 5528075 (1996-06-01), Burns
patent: 5889321 (1999-03-01), Culnane et al.
patent: 6051888 (2000-04-01), Dahl
patent: 6107678 (2000-08-01), Shigeta et al.
patent: 6407446 (2002-06-01), Kang et al.
patent: 403104263 (1991-05-01), None
Gebremariam Samuel A
Jorgenson Lisa K.
Lee Eddie
Munck William A.
STMicroelectronics Inc.
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