Method of eliminating or reducing poly1 oxidation at stacked gat

Details Method of eliminating or reducing poly1 oxidation at stacked gat Method of eliminating or reducing poly1 oxidation at stacked gat

1995-11-17

1998-08-04

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438923, H01L 218247

Patent

active

057892954

ABSTRACT:
A gate stack formation process directed toward reducing floating gate oxidation which influences tunnel oxide thickness and, therefore, discharge speed. On a substrate upon which is formed an oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer, only the second polysilicon layer and dielectric layer are etched. Source and drain regions are implanted through the first polysilicon layer. Subsequently, the first polysilicon layer is etched to form the full gate stack.

REFERENCES:
patent: 5464784 (1995-11-01), Crisenza et al.
patent: 5510284 (1996-04-01), Yamauchi

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