Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-03-02
2000-12-26
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438239, 438211, 438585, 36518501, H01L 21336
Patent
active
061658464
ABSTRACT:
The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.
REFERENCES:
patent: 5455790 (1995-10-01), Hart et al.
patent: 5464792 (1995-11-01), Tseng et al.
patent: 5526307 (1996-06-01), Yiu et al.
patent: 5530378 (1996-06-01), Kucharewski, Jr. et al.
patent: 5538923 (1996-07-01), Gardner et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5590274 (1996-12-01), Mehta
patent: 5661053 (1997-08-01), Yuan
patent: 5861347 (1999-01-01), Maiti et al.
patent: 6015732 (2000-01-01), Williamson et al.
Sharma, Umesh, et al.; "Vertically Scaled, High Reliability EEPROM Devices with Ultra-thin Oxynitride Films Prepared by RTP in N.sub.2 O/O.sub.2 Ambient"; International Electron Devices Meeting Technical Digest, San Francisco, CA; Dec. 13-16, 1992; pp. 17.5.1-17.5.4.
Fukuda, H.; et al.; "High-Performance Scaled Flash-Type EEPROMs with Heavily Oxynitrided Tunnel Oxide Films"; International Electron Devices Meeting Technical Digest; San Francisco, CA; Dec. 13-16, 1992; pp. 17.6.1-17.6.4.
Hattangady, S.V., et al.; "Ultrathin nitrogen-profile engineered gate dielectric films"; International Electron Devices Meeting Technical Digest; San Francisco, CA; Dec. 8-11, 1996; pp. 19.1.1-19.1.4.
Kooi, E., et al.; "Formation of Silicon Nitride at a Si-SiO.sub.2 Interface during Local Oxidation of Silicon and during Heat-Treatment of Oxidized Silicon in NH.sub.3 Gas"; Journal of the Electrochemical Society; vol. 123, No. 7; Jul. 1976; pp. 1117-1120.
Shankoff, T.A., et al.; "Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation"; Journal of the Electrochemical Society; vol. 127, No. 1; Jan. 1980; pp. 216-222.
Goodwin, C.A. and J.W. Brossman; "MOS Gate Oxide Defects Related to Treatment of Silicon Nitride Coated Wafers Prior to Local Oxidation"; Journal of the Electrochemical Society; vol. 129, No. 5; May 1982; pp. 1066-1070.
Voors, I.J., et al.; "Gate Oxide Reliability in a Sealed Interface Local Oxidation Scheme"; ESSDERC'89, 19th European Solid State Device Research Conference; Berlin; Sep. 11-14, 1989; pp. 361-365.
Tseng, Hsing-Huang and Philip J. Tobin; "A Double Sacrificial Oxide process for Smoother 150 .ANG. SiO.sub.2 Gate Oxide Interfaces"; The Electrochemical Society Extended Abstracts; vol. 92-1; St. Louis, Missouri; May 17-22, 1992; pp. 392-394.
Yoneda, Kenji, et al.; "Reliability Degradation Mechanism of Ultrathin Tunneling Oxide by Postannealing"; Journal of the Electrochemical Society; vol. 138, No. 7; Jul. 1991; pp. 2090-2095.
Yoneda, K., et al.; "Reliability Degradation Mechanism of the Ultra Thin Tunneling Oxide by the Post Annealing"; 1990 Symposium on VLSI Technology; Honolulu; Jun. 4-7, 1990; pp. 121-122.
Berg John E.
Carns Timothy K.
Kickel Bernice L.
Ransom John A.
Smythe, III John A.
Bowers Charles
Brewster William M.
Zilog Inc.
LandOfFree
Method of eliminating gate leakage in nitrogen annealed oxides does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of eliminating gate leakage in nitrogen annealed oxides, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of eliminating gate leakage in nitrogen annealed oxides will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-994023