Method of dual gate process

Details Method of dual gate process Method of dual gate process

2000-07-18

2002-07-09

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S275000, C438S287000, C438S591000, C438S770000, C438S775000, C257S369000, C257S411000

Reexamination Certificate

active

06417037

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating an integrated circuit device, and more particularly, to a method of fabricating an integrated circuit device having a dual gate oxide process.
(2) Description of the Prior Art
Dual gate oxide thicknesses are often required in making integrated circuit devices. For example, a thin gate oxide might be needed for a low voltage, low power dissipation device and a thick gate oxide may be needed for a high voltage, high speed, high current drive device built on the same integrated circuit. Typically, a first oxide layer is grown over a substrate. The first oxide layer is etched away in one area. A second oxide is grown where the first oxide was removed to form the thin gate oxide. The second oxide over the first oxide forms a thick gate oxide. However, the surface of the first oxide becomes rough after etchback, so the quality of the thick oxide may not be good. Since the first oxide contains no nitrogen, the thick oxide may not contain enough nitrogen to block boron penetration.
U.S. Pat. No. 5,882,993 to Gardner et al shows a dual oxide process in which a nitrogen-bearing impurity concentration within a portion of the substrate retards oxidation in that area. U.S. Pat. No. 5,918,133 to Gardner et al also teaches a nitrogen-bearing implant in one area that results in dual oxide thicknesses. U.S. Pat. No. 5,668,035 to Fang et al, U.S. Pat. No. 5,057,449 to Lowrey et al, U.S. Pat. No. 5,863,819 to Gonzalez, U.S. Pat. No. 5,244,843 to Chau et al, and U.S. Pat. No. 5,538,923 to Gardner et al show various dual gate silicon oxide methods.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for fabricating dual gate oxides in the fabrication of integrated circuits.
Another object of the present invention is to provide a method for forming dual gate oxides where both thin and thick gate oxide thicknesses can be controlled separately.
A further object of the invention is to provide a method for forming dual gate oxides of high quality where both thin and thick gate oxide thicknesses can be controlled separately.
In accordance with the objects of this invention, a method for forming dual gate dielectrics having high quality where both thin and thick gate dielectric thicknesses can be controlled separately is achieved. An isolation region separates a first active area from a second active area in a semiconductor substrate. A first gate dielectric layer is formed overlying the semiconductor substrate in the first and second active areas wherein the first gate dielectric layer has a first electrical thickness. The first gate dielectric layer in the second active area is removed. A second gate dielectric layer is formed in the second active area wherein the second gate dielectric layer has a second electrical thickness greater than the first electrical thickness and wherein the second gate dielectric layer is nitrided. A polysilicon layer is deposited overlying the first and second gate dieectric layers. The layers are patterned to form a first gate transistor in the first active area having the first gate dielectric layer thereunder and to form a second gate transistor in the second active area having the second gate dielectric layer thereunder.


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