Method of directionally trimming polysilicon width

Details Method of directionally trimming polysilicon width Method of directionally trimming polysilicon width

2006-08-15

2006-08-15

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21327, C257SE21623

Reexamination Certificate

active

07091077

ABSTRACT:
Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second layer of photoresist. The photoresist is trimmed to reduce the size of the exposed portions of the first patterned photoresist without reducing the size of the covered portions of the first patterned photoresist. The second layer of photoresist is removed. The selectively etched patterned first layer of photoresist is used as a process mask to define a structure in the underlying material. In a particular embodiment, the second photoresist covers endcap portions of gate photoresist. Directional trimming reduces the width of a polysilicon gate structure (i.e. gate length) over an active area of an FET, without reducing the length of original first patterned photoresist.

REFERENCES:
patent: 5922516 (1999-07-01), Yu et al.
patent: 6287904 (2001-09-01), Lee et al.
patent: 6787854 (2004-09-01), Yang et al.
patent: 2003/0049876 (2003-03-01), Mori et al.

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