Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2003-03-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06539522
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the testing of computer system designs by software simulation, and more particularly to a verification methodology for system-on-chip (SOC) designs which develops verification software which is re-usable throughout the development of a system-on-chip (SOC).
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip”, or SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design (for example, a core as described above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores functioning concurrently when interconnected as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core; simulation which includes a processor core tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the design.
However, inefficiencies in current verification methodologies exacerbate time pressures. Individual cores which are ultimately to be components of a SOC (“unit” cores) tend to be tested on an ad hoc, inconsistent basis. Thus, when it becomes necessary to test the cores interconnected as a system, additional software must be developed or the existing software modified to do so.
Additionally, once a design is implemented in hardware, it needs to be tested again. In existing verification methodologies, this hardware testing phase typically utilizes different software from that used in the simulation phase or further requires new software to be developed, further complicating and slowing verification.
A verification methodology is needed which addresses the problems noted in the foregoing.
SUMMARY OF THE INVENTION
A method according to the present invention develops verification software which is re-usable at all developmental phases of a system-on-chip design, from component core development to testing of a hardware implementation of the SOC.
A consistent coding methodology is used to develop software for applying test cases to individual cores at a component level. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Then, higher-level test control software is developed for controlling selected combinations of the already-existing test applications and supporting device drivers, to perform more complex test cases which exercise combinations of the component cores.
The software developed according to the above method may be used throughout the SOC development process, including during simulation phases and hardware bring-up of the SOC once physically implemented in silicon.
In a preferred embodiment, the verification software is written in a high-level programming language to make it portable across hardware platforms, including simulation platforms and the target SOC once physically implemented. A speed-up mode of operation is provided in which the embedded processor in the SOC design is replaced by a bus functional model which emulates the processor bus protocol to drive signals to other cores in the design. This speed-up mode allows the verification software to execute externally to the simulator, reducing simulation cycles.
The verification software developed may be stored and re-used by other projects. The method provides for the efficient verification of SOC designs because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores. Consequently, time-to-market for SOC products is significantly reduced.
REFERENCES:
patent: 5600579 (1997-02-01), Steinmetz, Jr.
patent: 5754764 (1998-05-01), Davis
patent: 5838948 (1998-11-01), Bunza
patent: 5841967 (1998-11-01), Sample et al.
patent: 6182258 (2001-01-01), Hollander
patent: 6378123 (2002-04-01), Dupenloup
patent: 6421251 (2002-07-01), Lin
Devins Robert J.
Ferro Paul G.
Herzl Robert D.
Kautzman Mark E.
Mahler Kenneth A.
Connolly Bove & Lodge & Hutz LLP
Do Thuan
Smith Matthew
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