Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-11-26
2004-11-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S017000
Reexamination Certificate
active
06813752
ABSTRACT:
TECHNICAL FIELD
The present invention generally pertains to the field of memory arrays. More particularly, embodiments of the present invention are related to a method of determining a charge loss activation energy for a memory array.
BACKGROUND ART
For some time it has been possible to fabricate memory devices such as flash memory that are both reprogrammable and retain their charge when power is removed. Such devices are highly desirable and have many applications from storing a computer system's BIOS to functioning as a memory for devices such as digital cameras. Typically, such memory devices may be reprogrammed hundreds of thousands of times.
Such devices may operate by storing a charge in a memory cell. For example, a typical flash memory cell may be programmed to hold a charge in a floating gate region of a transistor. Clearly, the ability of the memory cells to retain their charges is paramount to memory array performance. Such memory arrays may tend to lose their ability to hold charge, based on factors such as number of times reprogrammed, age, temperature, etc.
It is desirable to estimate the useful life of such memory arrays. In this fashion a manufacturer may provide a customer with data, such as a projected number of times the memory array may be reprogrammed, suggested ranges of operating temperatures, projected amount of time a device will retain its charge, etc. In order to provide such information, it is conventional to perform calculations using an activation energy for the particular product and conditions.
One such conventional technique is to test the device under high temperatures and then estimate the device's useful life under normal temperatures. Conventionally, this estimate may be based on the Arrhenius equation, which may be used to describe physio-chemical reaction rates. The Arrhenius equation may be expressed as:
A
=exp
[E
a
/k
(1
/T
u
−1
/T
e
)] Equation 1:
Where in equation 1, A is the acceleration factor, E
a
is the activation energy, k is Boltzmann's constant, T
u
is the temperature of normal use in Kelvin, and T
e
is the temperature during experimentation in Kelvin.
The activation energy will depend on characteristics of the mechanism being studied. In many cases, when a new technology is manufactured, the activation energy is merely estimated by using the value from a similar technology for which actual testing has been performed. However, the new technology may, in fact, have a very different activation energy. In some cases, the value of the activation energy is based on experimental evidence that may be decades old. Given the rapid changes in technique in fabricating semiconductor devices, relying upon data from a similar technology or old data is clearly suspect. Hence, any calculation for product lifetimes is unreliable.
Significantly, as the activation energy depends on the characteristics of the technology, the methodology to test for activation energy will be different for technologies with different characteristics. For example, flash memory or the like may have a failure mode associated with individual memory cells losing or gaining charge.
Thus, a need has arisen for a method to determine the activation energy for a memory device. A further need exists for a method for determining the activation energy for a memory device that stores charge, such as a flash memory. A need exists for determining the activation energy.
DISCLOSURE OF THE INVENTION
Embodiments of the present invention provide a method of calculating activation energy of a memory array. Embodiments provide a method of calculating activation energy of a memory array, as a function of program/erase cycles and differing technologies. The memory array may store charge, such as a flash memory. In one embodiment, the memory cells are capable of storing two separate bits by storing charge in two locations.
A method of determining charge loss activation for a memory array is disclosed. First, a first and a second memory array are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the first and the second memory arrays to experience an arbitrary amount of charge loss at respective first and second temperatures. Then, a charge loss activation energy is calculated, based on the respective bake times to lose the arbitrary amount of charge at the respective first and second temperatures.
In one embodiment, calculating respective bake times for the first and second memory arrays to experience the arbitrary amount of charge loss is performed as follows. The first memory array is baked at the first temperature for a plurality of time intervals. The charge loss is calculated for each of the time intervals. Then, the bake tile for the first memory array to experience the arbitrary amount of charge loss is calculated, based on the previous calculation. The second memory array may be processed in a similar fashion at the second temperature.
In another embodiment, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. A variety of different number of cycles are used, in various embodiments.
In yet another embodiment, various regions of the first or second memory arrays are programmed to a plurality of distinct delta threshold voltages before baking. For example, the difference in the transistor threshold voltages between the cells that are programmed to a first value and the transistor threshold voltages of cells that are programmed to a second value is programmed to a different value on different regions of the memory array.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
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Vigrass, William J., “Calculation of Semiconductor Failure Rates,” unknown date, unknown publication.
Hamilton Darlene G.
Hsia Edward
Randolph Mark W.
Tanpairoj Kulachet
Zheng Wei
Rossoshek Helen
Siek Vuthe
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