Method of detecting spatially correlated variations in a...

Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed

Reexamination Certificate

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C438S014000, C324S522000

Reexamination Certificate

active

06787379

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the testing of integrated circuit dies on a wafer during manufacture. More specifically, but without limitation thereto, the present invention relates to reducing the variation of a selected parameter in a production lot of integrated circuit die.
BACKGROUND OF THE INVENTION
An important issue in the manufacture of integrated circuits is detecting and rejecting integrated circuit die replicated on a silicon wafer that exhibit values of a selected parameter, for example, quiescent current (Iddq), that differ significantly from a mean value of the parameter. Integrated circuit die having values of the selected parameter that differ from the mean value by more than a selected threshold are called statistical outliers. Statistical outliers may pass performance testing, however, they may be more subject to premature failure and thus reduce the average service life of a production lot. Accordingly, a need exists for a method of detecting the statistical outliers.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of detecting spatially correlated variations includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common substrate; calculating a difference between a value of the selected parameter at a target location and that of an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a residual for the identical relative location.
In another aspect of the present invention, a process for reducing the variation of a selected parameter of an integrated circuit die includes measuring a selected parameter of each of a plurality of integrated circuit die replicated on a wafer substrate; calculating a difference between a value of the selected parameter at a target location and that of an identical relative location with respect to the target location for each of the plurality of integrated circuit die to generate a distribution of differences; calculating an absolute value of the distribution of differences; calculating an average of the absolute value of the distribution of differences to generate a residual for the identical relative location that is representative of an expected value range of the selected parameter at the identical relative location; and rejecting any of the plurality of integrated circuit die having a value of the selected parameter that lies outside the expected value range.


REFERENCES:
patent: 5889408 (1999-03-01), Miller
patent: 5889409 (1999-03-01), Kalb, Jr.
patent: 6239606 (2001-05-01), Miller
patent: 6342790 (2002-01-01), Ferguson et al.
patent: 2002/0102747 (2002-08-01), Muradian et al.
Thibeault, C., “On the Comparison of IDDQ and IDDQ Testing”, VLSI Test Symposium, 1999, Proceedings. 17th IEEE, pp. 143-150.*
Sabade et al. “Improved wafer-level spatial analysis for IDDQ limit setting”, Test Conference, 2001, Proceedings. International, pp. 82-91.*
Kruseman et al., “The future of delta IDDQ testing”, International Test Conference, 2001, pp. 101-110.*
Thibeault, C., “Improving delta-IDDQ-based test methods”, International Test Conference, 2000, pp. 207-216.

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