Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-12-12
2004-09-07
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C324S522000
Reexamination Certificate
active
06787379
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the testing of integrated circuit dies on a wafer during manufacture. More specifically, but without limitation thereto, the present invention relates to reducing the variation of a selected parameter in a production lot of integrated circuit die.
BACKGROUND OF THE INVENTION
An important issue in the manufacture of integrated circuits is detecting and rejecting integrated circuit die replicated on a silicon wafer that exhibit values of a selected parameter, for example, quiescent current (Iddq), that differ significantly from a mean value of the parameter. Integrated circuit die having values of the selected parameter that differ from the mean value by more than a selected threshold are called statistical outliers. Statistical outliers may pass performance testing, however, they may be more subject to premature failure and thus reduce the average service life of a production lot. Accordingly, a need exists for a method of detecting the statistical outliers.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of detecting spatially correlated variations includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common substrate; calculating a difference between a value of the selected parameter at a target location and that of an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a residual for the identical relative location.
In another aspect of the present invention, a process for reducing the variation of a selected parameter of an integrated circuit die includes measuring a selected parameter of each of a plurality of integrated circuit die replicated on a wafer substrate; calculating a difference between a value of the selected parameter at a target location and that of an identical relative location with respect to the target location for each of the plurality of integrated circuit die to generate a distribution of differences; calculating an absolute value of the distribution of differences; calculating an average of the absolute value of the distribution of differences to generate a residual for the identical relative location that is representative of an expected value range of the selected parameter at the identical relative location; and rejecting any of the plurality of integrated circuit die having a value of the selected parameter that lies outside the expected value range.
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Thibeault, C., “On the Comparison of IDDQ and IDDQ Testing”, VLSI Test Symposium, 1999, Proceedings. 17th IEEE, pp. 143-150.*
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Cota Kevin
Madge Robert
Whitefield Bruce
Fitch Even Tabin & Flannery
LSI Logic Corporation
Trinh Michael
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