Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-09
2005-08-09
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06928632
ABSTRACT:
Provided is a method of designing a semiconductor device in which power supply voltages can be applied individually and clock jitter is suppressed to avoid lowering of logic operation rate. Specifically, plural power supply lines (WL1) electrically connected to power supply bumps (BP1,BP2) are disposed in parallel to the lateral array of the power supply bumps (BP1,BP2), and power supply lines (WL2) of the lower layer which are electrically connected to the power supply lines (WL1) are disposed in parallel to each other so as to be orthogonal to the power supply lines (WL1) when viewed from above. Power supply voltages (V1, V2) are assigned to two power supply lines (WL1) that are nearest neighbors across an array of the power supply bumps (BP1), and power supply voltages (G1, G2) are assigned to two power supply lines (WL1) that are nearest neighbors across an array of the power supply bumps (BP2). The power supply lines (WL2) are disposed in parallel to each other so as to be orthogonal to the power supply lines (WL1) when viewed from above.
REFERENCES:
patent: 6034912 (2000-03-01), Isomura et al.
patent: 2002/0031032 (2002-03-01), Ooishi
patent: 2002/0141171 (2002-10-01), Bohr
patent: 405152302 (1993-06-01), None
Do Thuan
Renesas Technology Corp.
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