Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11019156
ABSTRACT:
A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
REFERENCES:
patent: 4613941 (1986-09-01), Smith et al.
patent: 5247455 (1993-09-01), Yoshikawa
patent: 5644500 (1997-07-01), Miura et al.
patent: 5847968 (1998-12-01), Miura et al.
patent: 5875117 (1999-02-01), Jones et al.
patent: 6011694 (2000-01-01), Hirakawa
patent: 6295634 (2001-09-01), Matsumoto
patent: 6510544 (2003-01-01), Matsumoto et al.
patent: 6584608 (2003-06-01), Kumada et al.
patent: 6643839 (2003-11-01), Nishio et al.
patent: 2003/0084418 (2003-05-01), Regan
patent: 2003/0226129 (2003-12-01), Nakagawa et al.
patent: 4-34951 (1992-02-01), None
patent: 9-91318 (1997-04-01), None
patent: 10-171856 (1998-06-01), None
patent: 2790090 (1998-06-01), None
patent: 3087669 (2000-07-01), None
patent: 2003-345844 (2003-12-01), None
Aiba Yoshitaka
Fujisawa Tetsuya
Nomoto Ryuji
Ozawa Kaname
Sato Mitsutaka
Dinh Paul
Fujitsu Limited
Parihar Suchin
Westerman, Hattori, Daniels & Adrian , LLP.
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