Method of depositing copper seed on semiconductor substrates

Details Method of depositing copper seed on semiconductor substrates Method of depositing copper seed on semiconductor substrates

2002-04-10

2003-11-04

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S625000, C438S627000, C438S628000, C438S629000, C438S637000, C438S638000, C438S644000, C438S648000, C438S654000, C438S656000, C438S666000, C438S668000, C438S672000, C438S675000, C438S678000, C438S685000

Reexamination Certificate

active

06642146

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to methods for forming a seed layer on an integrated circuit. More specifically, the methods include at least two operations. The first operation deposits seed material via PVD to provide some coverage, minimizing formation of overhang at feature openings. The second operation redistributes a portion of the seed material deposited in the first operation onto the sidewalls of the features, while simultaneously depositing additional material at least to the upper sidewalls.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer. (inter-metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching. In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below.
Presented in
FIGS. 1A-1H
, is a cross sectional depiction of a dual Damascene fabrication process. Referring to
FIG. 1A
, an example of a typical substrate,
100
, used for dual damascene fabrication is illustrated. Substrate
100
includes a pre-formed dielectric layer
103
(such as silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which; a diffusion barrier
105
has been deposited followed by inlaying with copper conductive routes
107
. Because copper or other mobile conductive materials have high diffusivities and readily diffuse into the ILD, the underlying silicon devices must be protected from metal ions (e.g., copper) that might otherwise diffuse into the silicon. Suitable materials for diffusion barrier
105
include tantalum, tantalum nitride, titanium nitride, and the like. In a typical process, barrier
105
is formed by a physical vapor deposition (PVD) process such as sputtering or a chemical vapor deposition (CVD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in damascene processes, as depicted in these figures. After fill of metal layer
107
(above the field) the excess metal is removed to the field level (as well as portions of diffusion barrier
105
on the field). This leaves metal inlay
107
exposed on the field region for construction of additional layers. The resultant partially fabricated integrated circuit
100
is a representative substrate for subsequent Damascene processing, as depicted in
FIGS. 1B-1H
.
As depicted in
FIG. 1B
, a silicon nitride or silicon carbide diffusion barrier
109
is deposited to encapsulate conductive routes
107
. Next, a first dielectric layer,
111
, of a dual damascene dielectric structure is deposited on diffusion barrier
109
. This is followed by deposition of an etch-stop layer
113
(typically composed of silicon nitride or silicon carbide) on the first dielectric layer
111
.
The process follows, as depicted in
FIG. 1C
, where a second dielectric layer
115
of the dual damascene dielectric structure is deposited in a similar manner to the first dielectric layer
111
, onto etch-stop layer
113
. Deposition of an antireflective layer
117
, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in
FIGS. 1D-1E
, with etching of vias and trenches in the first and second dielectric layers. First, vias
119
are etched through antireflective layer
117
and the second dielectric layer
115
. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias
119
is controlled such that etch-stop layer
113
is not penetrated. As depicted in
FIG. 1E
, in a subsequent lithography process, antireflective layer
117
is removed and trenches
121
are etched in the second dielectric layer
115
; vias
119
are propagated through etch-stop layer
113
, first dielectric layer
111
, and diffusion barrier
109
.
Next, as depicted in
FIG. 1F
, these newly formed vias and trenches are, as described above, coated with a conformal diffusion barrier
123
. As mentioned above, barrier
123
is made of tantalum, tantalum nitride, titanium nitride, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier
123
is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electroplating of the features with copper inlay. It is desirable to deposit a uniform conformal layer, but a major problem with conventional PVD methods of depositing seed layers is formation of “overhang” around the openings (top-most portions) of device features. See FIG.
1
G. Commonly, a high RF-bias sputter is used to deposit a metal (e.g. copper) seed layer,
124
, on diffusion barrier
123
. For example, Gopalraja et al. (U.S. Pat. No. 6,724,008) describe a method of via filling including a first step that uses a highly-ionized copper plasma with an RF bias applied to the wafer platen, followed by a more neutral deposition. Using such methods, generally more material is deposited onto the device feature surfaces at the top of the features than at the bottom. This is especially true with high aspect ratio (>3:1) features. Due to re-sputter of more heavily deposited material on the field, overhang,
126
, is formed at the aperture of trenches
121
. This overhang is problematic because in subsequent metal fill (e.g. electroplate), the overhang prevents complete fill of the features. This creates voids in the metal inlay that causes at best device unreliability or at worst unusable devices. As well, in the high-power low-pressure sputter first step, the wafer incurs a heavy heat load. This is particularly undesirable for low-k materials because it destroys or at least compromises the integrity of the dielectric layer or layers during the seed deposition.
There are conventional methods for addressing the problem of overhang. Iacoponi et al. (U.S. Pat. No. 6,228,754) describe a method in which the step coverage of a seed layer is improved by removing a portion of the seed around the feature opening using a sputter etch. This method only addresses removal of excess material at the top portion of the features. Improved step coverage is achieved by adding an excess of material to all surfaces and then removing a portion of the material at the topmost region of the features. This method does not address the issue of insufficient sidewall coverage (especially in the lower regions of device features) of the seed layer due to the inability of conventional PVD to reach difficult etch topography such as etch undercuts, bowed feature profiles, microtrenches, etc. Such problematic topographies are particularly prevalent in etched low-k materials. Liu et al. describe a multi-step PVD process where in each step a portion of the seed layer is deposited. This method deposits material in each step and the final depositi

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