Method of depositing a BSG layer

Details Method of depositing a BSG layer Method of depositing a BSG layer

2000-05-19

2002-02-05

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000, C427S578000, C427S535000

Reexamination Certificate

active

06344422

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to an improved method of depositing a boro-silicate-glass (BSG) layer onto a semiconductor structure. The method finds a valuable application in the fabrication of the buried plate in deep trench storage capacitors.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits and particularly in dynamic random access memory (DRAM) chips, deep trenches are extensively used. As known for those skilled in the art, in DRAM chips, an array transfer transistor, typically an insulated gate field effect transistor (IGFET) and a storage capacitor are associated to form the elementary memory cell. To date, due to scaling reduction effects, the storage capacitor is formed in a deep trench etched in the silicon substrate and includes a buried plate region to improve the capacitor dielectric robustness. In the course of the buried plate fabrication process, a layer of BSG is used as a hard mask during the trench formation. The step of removing said BSG layer is an essential part of the whole buried plate fabrication process.
A conventional buried plate fabrication process is described herein below in conjunction with FIG.
1
and
FIGS. 2A-2G
. All the processing steps are conducted in the so-called deep trench (DT) module.
FIG. 1
schematically illustrates the starting structure referenced
10
which basically consists of a P-type doped silicon substrate
11
coated with a 10 nm thick silicon oxide (SiO2) layer
12
and a 185 nm thick silicon nitride (Si3N4) pad layer
13
. These layers are typically deposited by a low pressure chemical vapor deposition technique (LPCVD).
Now turning to
FIG. 2A
, a 700 nm thick boro-silicate-glass (BSG) layer
14
is blanket deposited onto the P-type silicon substrate
11
by LPCVD as standard. For instance, the BSG layer
14
is deposited in a LAM 9800 tool, manufactured by LAM Research, Fremont, Calif., USA, using tri-ethyl-boron (TEB) and tetra-ethyl-boro-silicate (TEOS) gases according to the following operating conditions:
Temperature
750-850° C.
Pressure
1.1 Torr
TEB flow
2.6 ml/min (boron concentration: 5% in weight)
TEOS flow
4.4 ml/min
Next, a photoresist layer (not shown) is deposited onto structure
10
, which is baked, exposed and developed as standard according to the desired trench pattern. After resist patterning, the BSG, Si3N4 and SiO2 materials of layers
14
,
13
and
12
are sequentially etched, for instance, in the MxP chamber of an AME 5000 plasma etcher, a tool manufactured by Applied Materials, Santa Clara, Calif., USA with the following operating conditions.
Temperature
20° C.
Power
650 Watt
Pressure
95 mTorr
CF4 flow
50 sccm
CHF3 flow
35 sccm
Ar flow
100 sccm
(sccm denotes standard cubic centimeter per minute).
The resist mask is then stripped by ashing in a FUSION ACU, a tool manufactured by FUSION, Rockville, Md., USA using an 02/N2 mixture as standard. Now the deep trench is etched in the silicon substrate
11
. To that end, the BSG layer
14
is used as a hard mask during trench formation. For instance, the trench can be etched in a TEL 88 DRM tool, manufactured by TOKYO ELECTRON Limited, Yamanachi, Japan.
The following operating conditions are adequate.
Temperature
30° C.
Power
1300 Watt
Pressure
95 mTorr
HBr flow
150 sccm
NF3 flow
15 sccm
O2 flow
6 sccm
The BSG material has to be resistant to the silicon dry etch chemistry, in this case HBr and NF3 which are known to be very aggressive. For instance, with the operating conditions described above, less than 500 nm of BSG material are consumed in the etching of a trench having about 7-8 &mgr;m depth. At this stage of the buried plate fabrication, the structure
10
appears as shown in
FIG. 2A
with a deep trench
15
formed therein.
The BSG layer
14
must be stripped for reasons given later on. Typically, it is stripped with a conventional HF vapor wet process in an EXCALIBUR tool sold by FSI, Chaska, Minn., USA with N2 and HF flows of 60 l/min and 1.5 l/min respectively at 65° C. The etch rate is about 200 nm/min. The resulting structure is shown in FIG.
2
B. This wet etch process is essentially isotropic, so that an undesired undercut referenced
16
in
FIG. 2B
is formed on the SiO2 layer
12
side exposed in the trench
15
.
Because, this undercut
16
would be detrimental to the buried plate fabrication process, the Si3N4 layer
13
needs to be partially etched (14 nm) to avoid an excessive overhang above the SiO2 layer
12
and subsequent polysilicon fill problems. This step which is typically performed by wet chemistry is usually referred to as the pullback step in the technical literature. For instance, it can be performed in a MAGNUM SAT wet bench, a tol manufactured by SEMITOOL, Kalispell, Mont., USA using a HF/glycerol bath (1:25 ratio) wherein the HF is diluted in water (49/51 in volume %).
FIG. 2C
shows structure
10
at this stage of the buried plate fabrication. As apparent in
FIG. 2C
, thanks to the pullback step, the undercut effect has been clearly reduced.
Now, referring to
FIG. 2D
, a 400 nm thick arsenic silicon glass (ASG) layer
17
is first conformally deposited onto the structure
10
to entirely coat the trench
15
side wall. In turn, a 2 &mgr;m thick resist layer
18
is blanket deposited onto the structure
10
to fill the trench
15
.
The resist layer
18
is recessed down to a deepness of 1.3 &mgr;m in trench
15
using a O2/CF4 chemistry as standard in an AME 5000 plasma etcher mentioned above, so that the ASG layer
17
is exposed in the upper part of the trench.
Working conditions are:
CF4 flow
5 sccm
O2 flow
150 sccm
N2 flow
10 sccm
Power
600 Watt
Pressure
75 mTorr
This step is monitored by an etch end point system. First, in the resist planarization step, exposure of the Si3N4 etch stop layer
13
is detected by the CN radiation (388 nm). Next, the signal generated by an interferometer such as the MULTISEM 550, an equipment manufactured by SOFIE Inst., Arpajon, France, is monitored to measure the resist amount etched in the trench. The etch process is stopped when the desired depth of 1.3 &mgr;m is attained. This step which is thus only monitored by time is very critical to the whole BP fabrication process. A non-uniform BSG layer
14
thickness will be transferred to the resist level
17
A which is determining to the BP level definition.
The ASG material of layer
17
which thus becomes exposed is removed in a BHF bath (NH4F/HF/water in the 5:1:48 ratio in volume). Finally, the resist material remaining in trench
15
bottom is stripped as standard. The resulting structure is shown in FIG.
2
E.
A TEOS SiO2 layer
19
having a thickness of 50 nm is conformally deposited by LPCVD to coat structure
10
. Then, a thermal treatment is performed in a furnace at 950° C. to drive arsenic atoms out of the remaining ASG layer
17
into the substrate
11
to form the buried plate (BP) region
20
as illustrated in FIG.
2
F.
Now, the ASG and TEOS materials of layers
17
and
19
are removed from the trench
15
with a conventional wet process using a diluted HF (DHF) solution. As apparent in
FIG. 2G
, a dual nitride-oxide (NO) dielectric film
21
is conformally deposited onto the structure
10
to entirely coat its surface including the trench
15
sidewall. Finally, doped polysilicon is blanket deposited by LPCVD onto structure
10
to fill the trench
15
. The doped polysilicon layer referenced
22
in
FIG. 2G
is planarized by chemical-mechanical polishing using the Si3N4 pad layer
13
as an etch stop layer.
The BSG layer
14
has to be stripped before ASG layer
17
is deposited because it has a very non uniform thickness after the trench formation process described by reference to
FIG. 2A
(typically the BSG layer
14
thickness varies from 120 to 400 nm across the wafer). If it is not stripped, this non-uniformity will be transferred during the resist layer
18
recessing (described above by reference to
FIG. 2D
) so that the formation of the buried plate region
20
i

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