Method of defining small openings in dielectric layers

Details Method of defining small openings in dielectric layers Method of defining small openings in dielectric layers

2000-03-10

2002-06-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S622000, C438S623000, C438S637000, C438S638000, C438S639000, C438S666000

Reexamination Certificate

active

06406993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to semiconductor processing, and, more particularly, to a method for forming openings in a dielectric layer for conductive interconnections.
2. Description of the Related Art
There is a constant drive to reduce the channel length of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections.
Many modem integrated circuit devices are very densely packed, ie., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. The conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
As stated previously, an integrated circuit device is comprised of many thousands of transistors. An illustrative transistor
10
that may be included in such an integrated circuit device is shown in FIG.
1
. The transistor
10
is generally comprised of a gate dielectric
14
, a gate conductor
16
, and a plurality of source/drain regions
18
formed in a semiconducting substrate
12
. The gate dielectric
14
may be formed from a variety of dielectric materials, such as silicon dioxide. The gate conductor
16
may also be formed from a variety of materials, such as polysilicon. The source and drain regions
18
may be formed by one or more ion implantation processes in which a dopant material is implanted into the substrate
12
.
Next, a first dielectric layer
26
is formed above the transistor
10
, and a plurality of vias or openings
24
are formed in the first dielectric layer
26
. Thereafter, the vias
24
are filled with a conductive material, such as a metal, to form contacts
22
. In the illustrative transistor
10
shown in
FIG. 1
, the contacts
22
are electrically coupled to the source and drain regions
18
of the transistor
10
. Thereafter, a second dielectric layer
32
may be formed above the first dielectric layer
26
. Multiple openings
30
may be formed in the second dielectric layer
32
, and the openings
30
may thereafter be filled with a conductive material to form conductive lines
28
. Although only a single level of contacts and a single level of conductive lines are depicted in
FIG. 1
, there may be multiple levels of contacts and lines interleaved with one another. This interconnected network of contacts and lines allows electrical signals to propagate throughout the integrated circuit device. The techniques used for forming the various components depicted in
FIG. 1
are known to those skilled in the art and will not be repeated here in any detail.
In general, the various features of a semiconductor device, e.g., the gate electrode and the conductive interconnections of a typical field-effect transistor, are manufactured by a continual process of forming various layers of material, selectively removing, or patterning, portions of those layers, and, in some cases, forming additional layers of materials in opening defined in the layers. For example, to form a gate electrode of an illustrative field-effect transistor, a layer of material, such as polysilicon, may be deposited above a surface of a semiconducting substrate. Thereafter, portions of the polysilicon layer are removed, leaving what will become the gate electrode in place above the semiconducting substrate, i.e., the polysilicon layer is patterned to define a gate electrode.
The patterning of these various process layers is typically accomplished using known photolithography and etching process. In general, photolithography is a process in which a layer of photoresist, a material whose structure may be changed upon exposure to a light source, is formed above a process layer in which it is desired to form a feature of a semiconductor device. Essentially, the image that is desired to ultimately be formed in the underlying process layer will first be formed in the layer of photoresist by exposing portions of the photoresist layer to an appropriate light source. Following development of the photoresist layer, the remaining portions of the photoresist layer will be resistant to subsequent etching processes to be performed on the semiconductor device. The desired features of the semiconductor device are then formed in the underlying process layer by performing one or more wet or dry etching processes to remove the portions of underlying process layer that are not protected by the feature defined in the layer of photoresist.
However, as semiconductor feature sizes continue to decrease, it is desirable to form feature sizes to dimensions that are less than can be directly defined by standard photolithographic processes. In particular, due to the continual trend to produce more densely-packed integrated circuit devices, it is desirable to be able to form conductive interconnections to sizes smaller than can be achieved with traditional photolithographic techniques.
The present invention is directed to a method of making a semiconductor device that minimizes or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.


REFERENCES:
patent: 6074955 (2000-06-01), Lin et al.
patent: 6107189 (2000-08-01), Wald et al.

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