Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-04
2001-09-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S678000, C438S643000
Reexamination Certificate
active
06287968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing high performance semiconductor devices utilizing selective electroless plating processing and more specifically, this invention relates to a method of manufacturing high performance semiconductor devices utilizing a method of defining copper seed layers for selective electroless plating processing.
2. Discussion of the Related Art
As the performance of semiconductor devices have progressed to higher speeds, the use of aluminum as an interconnect material is causing a speed bottleneck Alternate materials such as gold (Au), silver (Ag), nickel (Ni), palladium (Pd), copper (Cu), and platinum (Pt) have all been explored. Of these, copper has become the preferred alternate replacement due to its low resistance and low cost. However, unlike aluminum, copper is not easily etched into wires or via plugs. An alternative method for manufacturing integrated circuits using multilevel copper interconnects has been developed that utilizes single damascene mask methodology.
As the price of semiconductor devices continues to decrease, there is pressure on the semiconductor manufacturing industry to minimize total cost. One of the major requirements to minimize total cost is to minimize the number of process steps. One method to minimize the number of processing steps is to combine the filling of conductive layers of metallization, for example, into both a trench and a via in a single step. Because current and future devices may have five or more layers of metallization (wire and via equal to one layer), combining the two will have a significant impact upon the total cost of the semiconductor device. Furthermore, the use of copper reduces contact resistance since this will eliminate every other barrier, glue, and seal layers between the current layer's via and wire, as shown in FIG.
1
.
FIG. 1
shows a semiconductor device
100
in which vias and wire interconnects have been formed by standard damascene methods. The semiconductor device
100
includes a layer
102
that could be a semiconductor substrate on and in which active devices (not shown) have been formed. The next layer
104
is a layer of interlayer dielectric in which metal structures, such as a wire
106
is formed. As is known in the semiconductor manufacturing art, a wire is used to connect one portion of a semiconductor device to another portion of the semiconductor device on the same layer. The wire
106
is typically formed in a trench formed in the layer of interlayer dielectric
104
. The walls of the trench are covered with a barrier layer
108
. The barrier layer
108
is typically formed from a metallic nitride material such as TiN or TaN. The trench is then filled with a conductive material. Conductive materials that can be used to fill the trench include tungsten, aluminum and copper. If copper is to be the conductive material to fill the trench, a seed layer
109
is formed on the barrier layer
108
. The seed layer is typically a thin layer of copper that may be sputtered onto the barrier layer
108
. A seal layer or hard mask layer
110
is formed on the surface of the layer
104
of interlayer dielectric. The layer
110
is a seal layer if the conductive material is to be copper. A seal layer prevents copper ions from diffusing into the surrounding material. A typical seal layer is made up of a material such as Si
z
N
y
or SiO
z
N
y
. A layer
112
of interlayer dielectric is formed on the layer
110
and metal structures such as via
114
are formed in the layer
112
of interlayer dielectric. The walls of via
114
are covered with a barrier layer
116
similar to barrier layer
108
. If via
114
is to be filled with copper, a seed layer
117
is formed on the barrier layer
116
. Via
114
is then filled with a conductive material. A seal layer or hard mask layer
118
is formed on the surface of the layer
112
of interlayer dielectric. The layer
118
is a seal layer if the via
114
is to be filled with copper. A layer
120
of interlayer dielectric is formed on the layer
118
. Trenches shown at
122
and
124
are formed in the layer
120
of interlayer dielectric. Barrier layers
126
and
128
are formed on the walls of the trenches
122
and
124
respectively and the trenches
122
and
124
are filled with conductive material. If the trenches
122
and
124
are to be filled with copper, seed layers
123
and
125
are formed on the barrier layers
126
and
128
. As is known in the semiconductor manufacturing art, trenches and vias are etched into a layer of interlayer dielectric material and a blanket layer of conductive material is then typically formed on the surface of the wafer and a polishing process, such as a chemical mechanical polishing process, is conducted to remove unwanted conductive material. As can be appreciated, the above process of forming individual-metal structures requires numerous steps.
FIGS. 2A-2C
show a method of eliminating several steps from the process of forming a semiconductor device as described above in conjunction with FIG.
1
. Like numerical designations denote like structures in the figures.
FIG. 2A
shows a partially completed semiconductor device
200
. The partially completed semiconductor device
200
shows layer
102
with metal structure
106
formed in layer
104
of interlayer dielectric. The metal structure
106
is formed by forming a via or trench in the layer
104
, forming a barrier layer
108
on the walls of the via or trench in the layer
104
, and forming a seed layer
109
on the barrier layer
108
if the via or trench in the layer
104
is to be filled with copper. The seal layer or hard mask layer
110
, the layer
112
of interlayer dielectric, the seal layer or hardmask layer
118
and the layer
120
of interlayer dielectric are formed on the layer
104
. The layer
110
is a seal layer if the subsequently formed vias and trenches are to be filled with copper. A series of masking and etching processes are then conducted to form vias, such as the via
114
and trenches, such as the trenches
122
and
124
, in the layers
104
,
110
,
112
,
118
, and
120
. A barrier layer
202
is formed on the walls of the vias and trenches. A seed layer
204
of copper is formed on the barrier layer
202
if via
114
and trenches
122
and
124
are to be filled with copper. There are several methods to deposit copper, however, only two of the methods can successfully form copper into the small geometries required for modern semiconductor technology. These two methods are chemical vapor deposition (CVD) and electroplating. Of the two, CVD is too expensive because of the gases used to supply the copper ions. Electroplating is the preferred method because electroplating can be done in batches, unlike a CVD process, which can only be done on one wafer at a time. When an electroplating process is utilized, the seed layer
204
of copper is formed on the barrier layer
202
. In this instance, a global deposition or sputtering of the conductive seed layer
204
is formed on the entire surface of the wafer. If the conductive material to be used is copper, the seed layer formation process consists of depositing or sputtering a thin layer of copper onto the entire wafer, which includes the sidewalls and bottom of the trenches and vias that have been formed in the semiconductor device
200
. The entire wafer is then submerged into a bath of ionic solution containing copper ions and an electroplating process causes a layer
206
of copper to be formed on the surface of the wafer. It is noted that the thickness of the layer
206
must be thick enough so that via
114
and trench
122
can be completely filled. Because some materials such as copper are difficult to polish, the process of planarizing the copper layer
206
is very difficult.
FIG. 2B
shows the partially completed semiconductor device
200
as shown in
FIG. 2A
after a polishing process to remove undesired portions of the layer
206
of copper and of the seed layer
204
. Howe
Scholer Thomas C.
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Bowers Charles
Kielin Erik
Nelson H. Donald
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