Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-13
2003-04-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S243000, C438S386000, C438S387000
Reexamination Certificate
active
06544838
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention is related to the fabrication of semiconductor devices, and more particularly, to the etching of high aspect ratio trenches in silicon substrates.
2. Description of the Related Art
The fabrication of deep trenches (DT) in silicon substrates is one method of making charge storage cells, referred to as deep trench capacitors. A deep hole of somewhat conical shape and an oval top cross section is etched into a silicon substrate by a commonly used dry etching method known as reactive ion etching (RIE). A dielectric film usually with a high dielectric constant is then deposited on the trench walls conformally. A doped polysilicon conductor is deposited to fill inside the trench, and a conductive region is formed in the silicon substrate on the other side of the dielectric material. The doped polysilicon conductor and the conductive region serve as the two capacitor plates.
The charge storage capacity of the dielectric film, called the capacitance, is inversely proportional to its film thickness and directly proportional to its area. Thus, the thickness of the film is kept to a minimum to the extent permitted by the process capability to form a continuous film on the trench walls. On the other hand, the inner surface area of the deep trench etched in silicon, is kept as large as possible within the constraints of the trench opening and mask thickness.
There is today an ever increasing need to make the deep trench opening smaller to accommodate more trenches in a given layout area of a chip on the substrate and, hence, to increase productivity and device performance. This reduction process is known to practitioners in the art as ground rule (GR) shrinking. The direct result of GR shrinkage is that the circumference or the perimeter of the DT ends up substantially reduced. To maintain the capacitance requirements of the DT capacitor, its depth must be constantly increased. Such a situation leads to very high aspect ratios, which is defined as the ratio of the depth of the etched structure relative to its width (i.e., if the structure is square or rectangular) or to its diameter (i.e., if the structure is circular or elliptical in shape). Etching of high aspect ratio trenches is made difficult due to reduction of etch rate with depth; and ultimately etching stops at very high aspect ratios.
The etching process in general, and the RIE process in particular, are strongly dependent on the aspect ratio of the structure to be achieved. A typical RIE process used for etching generally involves the deposition of oxide (SiO
2
) or nitride (Si
3
N
4
) films used as a hard mask. A photolithography process is then employed to open the holes in the hard mask. In subsequent steps, the trench holes are etched in the silicon substrate to form the deep trench capacitor. The process of forming deep trenches using RIE is well known in the art, and is described, e.g., in U.S. Pat. Nos. 5,605,600; 5,409,563; 5,629,226; 5,937,296, 5,891,807, and 5,112,771.
The deep trench silicon RIE process is relatively complex due to the need for etching anisotropic high aspect ratio features and due to continuous reduction of etch rate with increasing depths. Etching is performed in plasma equipment wherein gaseous species, usually containing Cl
2
, F, Br, and oxygen are ionized by applying radio frequency (RF) power in the capacitive or inductive mode. Etching is achieved by a combination of several mechanisms such as ion bombardment, ion assisted chemical etching and chemical etching (dominated by radicals). The profile control of DT is very important for processes like the filling of trenches with electrode material (e.g., polysilicon).
The RIE process, which may incorporate a controlled way of simultaneous deposition (of sidewall passivation film) and etching (of silicon trench and controlled etching of the passivation film), is tailored to control the profile and prevent isotropic etching. This objective is achieved by controlling the formation and the thickness of a passivation film on the walls of trenches as etching proceeds.
The role of passivation in deep trench etching and profile control has been described by Muller et al. in the aforementioned U.S. Pat. No. 5,605,600, wherein the effect of substrate temperature on the formation of passivation is described in detail. The process of high aspect ratio etching is also described by Cathey in the previously mentioned U.S. Pat. No. 5,409,563.
With the requirement of GR shrinkage, the control of DT sidewall (SW) passivation and inadequate mask selectivity have become important issues and an impediment in achieving deeper trenches. The depth to which a trench can be etched is limited by the mask thickness. In other words, for a given mask thickness the trench cannot be etched deeper than the thickness of the hard mask permits; otherwise the mask, particularly at the edge of the wafer, gets eroded causing black silicon which is a yield reducer. Achieving high selectivity between the silicon and the mask is at least as important as achieving high silicon etch rates.
The aforementioned task of forming storage capacitors with desired capacitance values finds its way into many applications, e.g., during the construction of certain classes of semiconductor devices, such as DRAMs (dynamic random access memory) which typically use two types of capacitors to store charge: i) capacitors formed in deep trench holes in crystalline silicon and ii) stacked capacitors. One important device parameter in these memory devices is the capacitance value of the memory cell. Higher values are preferred to increase the charge retention time in these cells. In the case of trench capacitor based devices, the capacitance value of a cell is proportional to the trench wall area, which in turn depends linearly upon the trench depth for a given trench opening dimension. As previously described, achieving large trench depths or larger wall area is therefore important in fabricating robust memory cells having large retention times.
Therefore, a need exists for a method for improving the fabrication of deep trench capacitors to increase trench depth and wall area to permit better retention times and to increase capacitance.
SUMMARY OF THE INVENTION
A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O
2
, HBr and NF
3
. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O
2
, HBr and SF
6
or F
2
.
Another method for etching trenches includes the steps of forming a plurality of dielectric layers on a silicon substrate to form a mask stack, and patterning the mask stack down to the silicon substrate to form an opening corresponding to a position where a deep trench is to be formed. Native oxide is removed from the silicon substrate at the position where the deep trench is to be formed and a trench is etched in the silicon substrate at the position. The etching of the trench includes plasma etching a tapered-shaped trench portion of the trench which narrows with depth in the silicon substrate by employing a first plasma chemistry mixture including O
2
, HBr and NF
3
and, in a same plasma reaction chamber, plasma etching an extended portion of the trench by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O
2
, HBr and SF
6
or F
2
. A controlled isotropic profile is formed thereby suitable for use with deep trench capacitors.
In other embodiments, the step of plasma etching the extended portion may include the step of resetting a Radio Frequency (RF) power of a plasma reaction chamber from a setting of the RF power for the step of forming a tapered-shaped trench portion.
Mathad Gangadhara S.
Naeem Munir D.
Ranade Rajiv
Braden Stanton
Kennedy Jennifer M.
Niebling John F.
LandOfFree
Method of deep trench formation with improved profile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of deep trench formation with improved profile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of deep trench formation with improved profile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3071608