Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-11-07
2000-08-22
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438638, 438740, 438743, 438744, 438970, 216 17, 216 18, 216 41, H01L 214763
Patent
active
061071919
ABSTRACT:
The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.
REFERENCES:
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5891799 (1999-04-01), Tsui
Lucent Technologies - Inc.
Niebling John F.
Zarneke David A
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