Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-26
2004-06-08
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S008000, C438S633000, C438S692000, C438S697000
Reexamination Certificate
active
06746958
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of controlling the duration of an endpoint polishing process in a multistage polishing process.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In modem integrated circuit devices, millions of transistors are formed above a surface of a semiconducting substrate. To perform their intended functions, these transistors, or groups of transistors, are electrically coupled together by many levels of conductive interconnections, i.e., conductive metal lines and plugs. These conductive lines and plugs allow electrical signals to propagate throughout the integrated circuit device.
In general, these conductive interconnections are formed in layers of insulating material, e.g., silicon dioxide, HSQ, or other materials that may have a dielectric constant less than approximately 4. The insulating materials electrically isolate the various conductive interconnections and tend to reduce capacitive coupling between adjacent metal lines when the integrated circuit device is in operation. Moreover, modem integrated circuit devices are very densely packed, i.e., there is very little space between the semiconductor devices, as well as between the conductive metal lines. Accordingly, the amount of insulating material positioned between adjacent metal lines, and other surrounding conductive structures, both above and below the metal lines, is very important.
As the demand for high performance integrated circuit devices continues to increase, circuit designers and manufacturers look for ways to improve device performance. Recently, copper has become the material of choice for conductive interconnections for high performance integrated circuit devices, e.g., microprocessors, due to its lower resistance as compared to, for example, aluminum.
Typically, a layer of insulating material will be formed on or above a semiconducting substrate. Thereafter, a plurality of openings will be formed in the layer of insulating material using known photolithographic and etching techniques. Then, after the formation of a barrier metal layer, e.g., tantalum, a layer of copper will be formed above the insulating layers and in the openings in the insulating layer by performing an electroplating process. Next, the excess copper material positioned outside of the openings in the insulating layer is removed by performing one or more chemical mechanical polishing operations.
Such chemical mechanical polishing operations may involve polishing tools in a sequence of polishing operations. For example, the bulk of the excess copper may be removed during an initial, timed polishing process. The removal rate during the initial timed etch process may be relatively high. Thereafter, an endpoint etch process may be performed to remove the remaining copper material. The removal rate during this endpoint process may be relatively low. Additional polishing operations may be performed on the device after these steps are performed.
Problems may arise when the incoming layer of copper is thicker or thinner than anticipated. For example, if the incoming thickness of the layer of copper is thicker than anticipated, the initial timed polishing process may not remove enough of the incoming layer of copper. As a result, the endpoint process may be performed for too long of a duration. As a result, manufacturing efficiencies are reduced and the overall output of the manufacturing facility may be reduced. Alternatively, if the layer of copper is thinner than anticipated, the initial timed polishing operation may remove too much of the copper layer, to the point that the operations may unnecessarily consume too much of the underlying insulating layer.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of controlling chemical mechanical polishing operations to control the duration of an endpoint polishing process. The method comprises providing a wafer having a layer of copper formed thereabove, performing a first timed polishing operation for a duration (t
1
) on the layer of copper at a first platen to remove a majority of the layer of copper, and performing an endpoint polishing operation on the layer of copper at a second platen to remove substantially all of the layer of copper remaining after the timed polishing operation performed at platen
1
. The method further comprises determining a duration (t
2
ept
) of the endpoint polishing operation performed on the layer of copper at the second platen, and determining, based upon a comparison between the determined duration (t
2
ept
) of the endpoint polishing operation at platen
2
and a target value for the duration of the endpoint polishing operations, a duration (t
1
) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen. In another embodiment, the invention further comprises modifying, based upon a variance between the determined duration (t
2
ept
) of the endpoint polishing operation and a target value for the duration (t
2
ept
) of the endpoint polishing operation, the duration (t
1
) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen.
REFERENCES:
patent: 6274478 (2001-08-01), Farkas et al.
Hewett Joyce S. Oey
Marxsen Gerd Franz Christian
Toprac Anthony J.
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Pham Thanhha S
Williams Morgan & Amerson P.C.
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