Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-10-01
2004-07-20
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S737000, C438S947000
Reexamination Certificate
active
06764946
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of integrated circuit manufacture and, more particularly, to a method of reducing the prominence of line edge roughness in a photo resist line and then, subsequently, in a layer to be etched that underlies the photo resist line.
BACKGROUND
The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. For instance, patterns can be formed from a photo resist layer by passing light energy through a mask (or reticle) having an arrangement to image the desired pattern onto the photo resist layer. As a result, the pattern is transferred to the photo resist layer. In areas where the photo resist is sufficiently exposed and after a development cycle, the photo resist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, etc.). Portions of the photo resist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer. The exposed portions of the underlying layer can then be etched (e.g., by using a chemical wet etch or a dry reactive ion etch (RIE)) such that the pattern formed from the photo resist layer is transferred to the underlying layer. Alternatively, the photo resist layer can be used to block dopant implantation into the protected portions of the underlying layer or to retard reaction of the protected portions of the underlying layer. Thereafter, the remaining portions of the photo resist layer can be stripped.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. As a result, there is a corresponding need to increase the resolution capability of lithography systems. To accomplish this goal, relatively short wavelengths (e.g., less than about 258 nm) have been used for the illumination light source. In conjunction with these relatively short wavelengths, ultra thin resists (UTR) have been used. For example, many applications include the use of photo resist layers that have a thickness of about 0.1 micron or thinner.
As the critical dimension (CD) of lines formed using UTRs becomes smaller (e.g., about 0.25 microns and smaller), line edge roughness (LER) of the lines increases. In some instances, LER becomes significant enough to effect device performance and lead to unacceptable ICs formed on the wafer. For example, 0.18 micron lines formed using conventional lithographic techniques will tend to have noticeable LER, 0.12 to 0.13 micron lines will tend to exhibit significant LER, 0.10 micron lines will tend to have very poor LER and 0.06 micron lines will tend to have an extremely poor LER.
Accordingly, there exists a need in the art for improved lithography process techniques to control LER.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of forming an integrated circuit line on a wafer using a lithographic technique. The method can includes providing the wafer, the wafer including a substrate and, over the substrate, each of a photo resist layer and an underlying layer to be processed under the photo resist layer; exposing and developing the photo resist layer to form a photo resist line, the photo resist line having a line width smaller than a desired line width of the integrated circuit line; coating the photo resist line with a reactive coating; and reacting the photo resist line with the coating to form a mask line having a line width corresponding to the desired line width of the integrated circuit line and with a smaller line edge roughness (LER) than of the photo resist line.
REFERENCES:
patent: 6174818 (2001-01-01), Tao et al.
patent: 6486058 (2002-11-01), Chun
patent: 6514672 (2003-02-01), Young et al.
patent: 2003/0027080 (2003-02-01), Lu
patent: 19990122188 (1999-12-01), None
Toyoshima, et al, 0.1 &mgr;m Level Contact Hole Pattern Formation with KrF Lithography by Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS), IEEE 1998, IEDM 98-333, pp. 12.5.1-12.5.4.
RELACS Resolution Enhancement Lithography Assisted by Chemical Shrink AZ R500, Pure D.I. Water Developable RELACS Coating, Updated on Jun. 28, 2002, Version 05. Clariant Japan K.K., BU Electronic Materials.
Advanced Micro Devices , Inc.
Dang Phuc T.
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Method of controlling line edge roughness in resist films does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of controlling line edge roughness in resist films, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlling line edge roughness in resist films will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3219914