Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2002-05-15
2004-01-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S486000, C438S532000
Reexamination Certificate
active
06682992
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor manufacturing; more specifically, it relates to semiconductor devices fabricated with controlled grain size polysilicon structures and a method of fabricating semiconductor devices having controlled grain size polysilicon structures.
BACKGROUND OF THE INVENTION
Polysilicon layers are frequently used in forming the emitter of semiconductor devices such as bipolar transistors, the gate electrode of field effect transistors (FETs) and the resistive element in thin film and damascened resistors.
In the case of bipolar transistors and particularly SiGe bipolar transistors having low emitter resistance, high germanium base concentration and narrow base width are highly desirable in high performance devices. However, these conditions can result in extremely high current gain (b). Conventionally, emitter resistance has been lowered and base current increased (resulting in lower b) by reducing the thickness of the emitter/base interface oxide. However, there is a limit to how thin the interface oxide can become and still effectively prevent epitaxial realignment.
In the case of FET and resistor devices, as polysilicon gate electrode (polysilicon lines for resistors) width and height are reduced, depletion of dopant in the gate electrode due to channeling during ion implantation as well as dopant diffusion effects with reductions in activation anneal times and temperatures, results in non-uniform doping of the polysilicon gate (or line).
A method other than reducing the thickness of the emitter/base interface oxide thickness to control emitter resistance and base current in bipolar transistors and to overcome depletion of dopant in the gate electrode in FETs and to improve control of thin film and damascened resistors is required if the trend to smaller feature size and improved device performance is to continue.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of modulating grain size in a polysilicon layer comprising: forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.
A second aspect of the present invention is a method of fabricating a bipolar transistor having a collector, a base and a polysilicon emitter comprising; implanting a dopant species and a polysilicon grain size modulating species into the polysilicon emitter; and annealing the implanted polysilicon emitter.
A third aspect of the present invention is a method of modulating a dopant species concentration profile in a polysilicon layer of a device comprising; implanting a dopant species and a polysilicon grain size modulating species into the polysilicon layer; and annealing the implanted polysilicon layer.
A fourth aspect of the present invention is a bipolar transistor comprising; a collector; a base; and a polysilicon emitter containing a dopant species and a polysilicon grain size modulating species.
A fifth aspect of the present invention is a device comprising; a polysilicon layer forming at least a portion of a structure of the device; and the polysilicon layer containing a dopant species and a polysilicon grain size modulating species.
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Carbone et al., “Correlation of Ellipsometric Volumne Fraction to Polysilicon Grain Size from Transmission Electron Microscopy”, Sep. 1999, IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, pp. 359-367.*
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Geiss Peter J.
Greco Joseph R.
Kontra Richard S.
Lanning Emily
Malsawma Lex H.
Sabo William D.
Schmeiser Olsen & Watts
Smith Matthew
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