Method of controlling gate dopant penetration and diffusion...

Details Method of controlling gate dopant penetration and diffusion... Method of controlling gate dopant penetration and diffusion...

1999-03-02

2001-01-16

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S369000, C438S532000, C438S542000, C438S592000, C438S621000, C438S659000

Reexamination Certificate

active

06174807

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and. more particularly, to a method of controlling gate dopant penetration and diffusion in a multi-layered dual-doped polysilicon structure and in CMOS devices fabricated therefrom.
BACKGROUND OF THE INVENTION
Gate dopant penetration and lateral diffusion in a multi-layered dual-doped polysilicon structure adversely affects the fabrication yield and the performance of integrated circuits constructed from such structures. To prevent gate dopant penetration during formation of n+ and p+ polysilicon gates, two photoresist masks are typically applied and removed at different stages of the fabrication process which, of course, increases the expense of the fabrication process. While the thermal budget (i.e., the temperature and time fabrication parameters) may be reduced to limit the amount of dopant penetration, reducing lateral diffusion of gate dopants during subsequent processing steps, i.e., steps performed after the n+ and p+ polysilicon gates have been formed, presents a more vexing problem. Although some Boron diffusion may be acceptable, it is desirable to minimize the amount so that the performance of the semiconductor device manufactured from the structure is not adversely effected (i.e., too much Boron diffusion will change the characteristics of the n+ type polysilicon and hence the NMOS device (transistor)). Here too the thermal budget may be reduced to address gate dopant diffusion. In addition, Tungsten-Silicide or Tungsten alone may be eliminated from the structure. However, this results in a high gate sheet resistance.
There thus exists a need in the art for a method of fabricating a multi-layered dual-doped polysilicon structure that overcomes the above-described shortcomings of the prior art.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.
In accordance with the method of the present invention, a multi-layered structure having an n-tub region and a p-tub region in a substrate and a polysilicon layer disposed thereabove is formed by applying a gate dopant mask over the polysilicon layer above the n-tub region. N+ polysilicon is formed by introducing n+ gate dopant into the unmasked polysilicon layer above the p-tub region of the substrate. A gate dopant barrier is formed by implanting Nitrogen into the polysilicon layer to form a Nitrogen-rich region above the p-tub region (into the n+ polysilicon). The barrier blocks penetration of p+ gate dopant into the n+ polysilicon during formation of the p+ polysilicon. Thereafter, the gate dopant mask is removed and a meta-lsilicide is applied over the polysilicon layer. A p+ gate dopant is introduced into the metal-silicide and the structure is exposed to a rapid thermal anneal process to drive the p+ gate dopant into the polysilicon layer above the n-tub region of the substrate, i.e. to form p+ polysilicon in the polysilicon layer above the n-tub region. The n+ gate dopant may be Arsenic and/or Phosphorous, and the p+ gate dopant is preferably Boron.
The semiconductor device of the present invention includes a multi-lavered structure having an n-tub region and a p-tub region in a substrate and a polysilicon layer disposed thereabove. N+ polysilicon is defined in the polysilicon layer above the p-tub region, and p+ polysilicon is defined in the polysilicon layer above the n-tub region. A gate dopant barrier implanted in the polysilicon above the p-tub region (in the n+ polysilicon) minimizes introduction of p+ gate dopant into the n+ polysilicon gate during formation of the p+ polysilicon. The barrier also reduces p+ gate dopant (Boron) and n+ gate dopant (Arsenic or Phosphorous) migration during fabrication of the semiconductor device.
Other objects and features of the present invention will become apparent from the following detailed description. considered in conjunction with the accompanying drawing figures. It is to be understood, however, that the drawings, which are not to scale, are designed solely for the purpose of illustration and not as a definition ot the limits of the invention, for which reference should be made to the appended claims.


REFERENCES:
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patent: 4554726 (1985-11-01), Hilllenius et al.
patent: 4851257 (1989-07-01), Young et al.
patent: 5278096 (1994-01-01), Lee et al.
patent: 5837601 (1998-11-01), Matsumoto
patent: 5851922 (1998-12-01), Bevk et al.

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