Method of controlling FSG deposition rate in an HDP reactor

Details Method of controlling FSG deposition rate in an HDP reactor Method of controlling FSG deposition rate in an HDP reactor

2000-12-27

2002-06-11

Ghyka, Alexander G. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S784000, C438S788000

Reexamination Certificate

active

06403501

ABSTRACT:

BACKGROUND
1. Field of Invention
The present invention relates to semiconductor processing, and in particular, to chemical vapor deposition in a high density plasma reactor.
2. Related Art
High density plasma (HDP) chemical vapor deposition (CVD) processes are used in the fabrication of integrated circuits for depositing films on a substrate. One application of an HDP CVD process is to fill gaps on a semiconductor device having high aspect ratios (e.g., about 2.5:1 or greater) and close spacing (e.g., about 0.25 &mgr;m or less). Existing HDP CVD processes typically employ deposition with a process gas mixture that includes oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric etching and deposition.
In an HDP process, RF bias is applied to a wafer substrate in a reaction chamber. As a result, the flux of deposition precursors is perpendicular to the wafer, and the net film growth occurs perpendicularly to the bottom of the feature. Some of the gas molecules (particularly argon) are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface. As a result, dielectric material deposited on the wafer surface is simultaneously sputter-etched to help keep gaps open during the deposition process, which allows higher aspect ratio gaps to be filled.
An important goal in HDP deposition of these and other layers is to deposit a film of uniform thickness across the surface of a substrate and across different batches of substrates. One factor mitigating against uniform deposition is dopant concentrations in the processing environment. In HDP CVD processes, this is important because the reactor can act either as a sink or a source for dopants that affect the growth rate on the wafer.
A typical HDP CVD reactor includes a reaction chamber having an upper lid or dome, typically made of a ceramic such as aluminum oxide (Al
2
O
3
). During the deposition process, process gases are introduced into the chamber, and a plasma of the processing gases is generated within the chamber to effectuate chemical vapor deposition onto the substrate. However, the deposition typically occurs on all the surfaces exposed to the processing gases, including the interior surfaces of the chamber. If the dopant concentration of the processing environment is not in equilibrium, a shift in deposition rate can occur. This shift in deposition rate due to changing reactor conditions can be as high as 500 Å/min.
When the reactor is in an idle state, an argon and oxygen plasma, Known as an “idle plasma”, is used maintain the reactor temperature. The oxygen in the idle plasma will deplete the fluorine species adsorbed to the sidewalls over time. This creates an environment that is not in equilibrium. For example, when depositing fluorine-doped silicon oxide layers, such as fluorosilicate glass (FSG), a reactor in an idle condition has been depleted of the dopants adsorbed to the chamber surfaces. When FSG deposition begins again, SiF species are adsorbed again to the reactor walls. This retards the deposition on the substrate surface. As the reactor approaches an equilibrium state, the deposition rate on the substrate rises and eventually levels off. Depending on the reactor conditions, the dopant concentration, and the target thickness of the FSG on the wafer, 200 or more deposition sequences may be required to reach a steady state. Once the reactor is in a steady state, processing must be continuous or the idle plasma will again begin to deplete the adsorbed dopants in the reactor causing the deposition rate on subsequent wafers to be reduced.
Accordingly, it is desirable to deposit a dielectric film without the problems discussed above that are associated with conventional techniques.
SUMMARY
In accordance with one aspect of the present invention, prior to beginning deposition of doped dielectric layers on wafers, a high density plasma (HDP) chemical vapor deposition (CVD) chamber is first conditioned by forming a layer of the doped material within the chamber walls. This conditioning quickly brings the chamber to an equilibrium state so that subsequent deposition of the doped dielectric material onto wafers yields consistent deposition rates because dopants are already adsorbed to the chamber walls. Approximately constant deposition rates can be maintained as long as the reactor is running and depositing layers onto wafers. However, if the deposition is halted for a certain amount of time, e.g., 20 minutes, and the reactor becomes idle, the chamber is plasma cleaned and a thin layer of the doped material is deposited onto the chamber walls. Periodically, for example, every 12 hours, the chamber is plasma cleaned and the thin layer is re-deposited. This allows consistent deposition rates even when the reactor has been idle for prolonged periods of time.
In one embodiment, initial conditioning, such as after a wet clean, is carried out by introducing a gas containing silicon fluoride (SiF
4
), argon, and oxygen into the chamber to form a fluorosilicate glass (FSG) approximately 10 to 30 &mgr;m thick. After idle (e.g., 20 minutes without processing), the chamber is plasma cleaned and a thin FSG layer of approximately 1 to 3 &mgr;m is deposited. The plasma clean and deposition of the thin FSG layer is repeated periodically, e.g. every 12 hours, to maintain the chamber in an equilibrium state.
The present invention will be more fully understood when taken in light of the following detailed description taken together with the accompanying drawings.


REFERENCES:
patent: 6121161 (2000-09-01), Rossman et al.
patent: 6200911 (2001-03-01), Narwankar et al.

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