Method of controlling etch bias with a fixed lithography pattern

Details Method of controlling etch bias with a fixed lithography pattern Method of controlling etch bias with a fixed lithography pattern

1996-12-31

1999-08-03

Smith, Lynette F.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

216 59, 216 84, C03C 1500, C03C 2506

Patent

active

059337591

ABSTRACT:
The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer. Polymer sidewalls protect the photoresist, polish stop layer (or etch hard mask layer), and oxide layer during the third etch step thereby improving the etch selectivity and etch bias control. The third etch step completes the formation of the trench by etching the substrate.

REFERENCES:
patent: 5116460 (1992-05-01), Bukhman

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