Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-12-29
2001-01-30
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S775000, C257S784000
Reexamination Certificate
active
06181011
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to dimensions and ratios of dimensions of features of elements of integrated circuit (IC) chips, primarily metal lines, but also including poly-silicon or other device features.
BACKGROUND OF THE INVENTION
Modern integrated circuit (IC) chips comprise a semiconductor substrate and a large number of active devices (e.g., transistors, gates) which are formed in the substrate and which are interconnected to one another with conductive traces (lines). The traces typically are formed either of metal or of polysilicon, and resemble a ribbon having a width dimension (W) and a thickness dimension (T). A large number of such conductive traces are typically present on a given IC chip, and are spaced a distance (S) from one another.
As a general proposition, the trend is towards forming features, including conductive traces (e.g., metal lines), which are smaller and smaller, permitting an increasing number of active devices to be interconnected in increasingly complex manners on semiconductor devices, thereby enabling enhanced functionality and increased operating speeds. In other words, reducing device dimensions allows higher density logic integration and faster speeds. This has been the primary motivation of plunging into sub-micron dimensions. The scaling trend towards smaller-and-smaller dimensions leads to smaller feature size, complex device physics, increase of chip size, increase in operating frequencies and increase in chip complexity. The physical parameters affected are decrease of gate and metal width, spacing and thickness, decrease of dielectric thickness and increase of interconnect length. The scaling impact on the electrical parameters is potentially an increase of total capacitance, with increasingly dominant coupling effects, increase of interconnect resistance and the inductance effects at chip level. Interconnect effects, mainly delay, starts playing the dominant role in deciding the performance of the circuit at small geometries, such as 0.35 &mgr;m and below. By plotting wire-length distribution over feature size and die size, it is evident that signal delay is dominated by RC interconnect peaks as we go to lower feature size and higher die size.
Scaling is not done by the same factors for all the variables i.e. length, width, thickness of gate and metal layers, dielectric thickness and voltage are not scaled by the same factors. It can be shown that in some cases it is not allowed by available technology, for example, some dimensions are not practicable by current lithography, diffusion, etc. limitations and other cases it will not lead to high performance ICs.
The technology solutions available to solve this problem are:
1) Increase in the number of layers, which will result in shorter interconnects;
2) Using higher conductivity materials like copper, since resistance is inversely proportional to conductivity; and
3) Using materials with low dielectric constant like polyimide.
All the above solutions leads to higher cost for production (fab) and design.
Utilizing what is now considered to be “old” technologies, feature sizes limited to on the order of >0.5 &mgr;m resulted, and resemble a wide ribbon having a width dimension (W) which is substantially in excess of the thickness dimension (T) along the length of trace for older technologies. In other words, typically W>>T, or the cross-sectional area ratio W:T is >>1.
Newer technologies, facilitating smaller geometries (on the order of 0.35 &mgr;m feature size), permit near one-to-one (1:1) ratio of width-to-thickness, or tall thin cross-sectional structures over the length of a conductive trace.
DISCUSSION OF THE PRIOR ART
Integrated circuit (IC) chips, such as those found in computers and electronic equipment, often contain up to millions of transistors and other circuit elements fabricated on a single chip. To achieve a desired functionality, a complex network of signal paths must typically be routed to interconnect the circuit elements with one another. Efficient routing of signals across a chip becomes increasingly difficult as integrated circuit complexity grows. To ease this task, interconnection wiring, which not too many years ago was limited to a single level of metal conductors (traces, lines), on today's devices may contain a plurality (e.g., five or more) stacked levels of interconnection wiring of densely-packed conductive (typically metallic) traces separated by layers of insulating (dielectric) material.
Modern interconnect (wiring) layers typically are formed by one of two general techniques. In a first technique (“deposit-pattern-etch”), a conductive film (layer) is “blanket” deposited over a preferably planar underlying insulation layer which usually contains vias, or through holes, allowing the conductive film to contact underlying circuit structures where electrical connections to those circuit structures are required. Portions of the conductive film are then selectively etched away, in any of a number of known ways typically using a mask pattern (and an etchant), leaving a network (pattern) of separate conductors, each having a similar thickness, and each having a generally rectangular cross-section extending across the underlying insulating layer. Prior to forming a subsequent wiring layer, the conductors are covered with an interlevel dielectric layer and the processes of depositing and patterning another conductive film are repeated, as required.
A second technique for forming interconnection layers is known as the “damascene” process, so-named as being reminiscent of an inlaid metal technique perfected in ancient Damascus for decorating swords and the like. The damascene technique involves etching a network (pattern) of channels (trenches) into the top surface of an insulating (dielectric) layer which preferably has been planarized, such as by chemical-mechanical polishing, and then depositing a conductive film over the etched insulating layer, thereby filling the channels with conductive material. Then, excess conductive material which is not in the channels, but rather is on the top surface of the insulating layer, is removed, such as by chemical-mechanical etching, which also helps planarize the insulating layer in preparation for applying, etching channels in and filling with conductive material a subsequent insulating layer. This process was described in the patent literature as early as 1990, and reference is made to U.S. Pat. No. 4,944,836, which is incorporated in its entirety by reference herein.
The damascene process is particularly attractive for sub-micron interconnect fabrication. Chemical etching processes are well known which can anisotropically (i.e., unidirectionally) etch insulating material such as silicon dioxide to form high-aspect ratio (i.e., deep and narrow) channels (trenches) with vertical sidewalls. Materials such as low resistivity, high copper content conductive materials which are not readily patterned by masking and etching can be employed. And the damascene, by virtue of the polishing step between the application of each layer of conductive lines, results in highly planarized interconnection layers, a feature which is desirable for making multilevel (multi-layer) interconnections.
As a general proposition, the harder the conductive material, the better the damascene process works. It has been noted that when working with soft materials such as Al—Cu alloys, the polishing step can result in scratching, smearing, corrosion and dishing of the conductive material, removing conductive material in the channels to below the level of the top surface of the insulating layer. This problem was addressed in U.S. Pat. No. 5,262,354, incorporated in its entirety by reference herein, which proposed depositing the soft metal such that the channels are underfilled (filled to between a few hundred nanometers (nm) and a few hundred Angstroms (Å) of the top surface of the insulating layer), then “capping” the soft material with a harder material such as tungsten before polishing. This app
Muthukumaraswamy Kumaraguru
Rostoker Michael D.
Clark Sheila V.
Kawasaki Steel Corporation
Linden Gerald E.
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