Method of complementary metal-oxide semiconductor

Details Method of complementary metal-oxide semiconductor Method of complementary metal-oxide semiconductor

1999-01-25

2001-05-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000, C438S268000

Reexamination Certificate

active

06232162

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87117233, filed Oct. 19, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating semiconductor devices. More particularly, the present invention relates to a method of fabricating a complementary metal-oxide semiconductor (CMOS).
2. Description of Related Art
A complementary metal-oxide semiconductor (CMOS) is composed of an N-type MOS and a P-type MOS. Less electrical energy is needed in operating the CMOS transistor, therefore, the CMOS is mostly used in very large scale integration (VLSI), and also in ultra large scale integration (ULSI).
FIG.
1
A through
FIG. 1E
are schematic, cross-sectional views showing a conventional method of fabricating a complementary metal-oxide semiconductor. In
FIGS. 1A
to
1
D, the part of the wafer indicated by the reference numeral
100
shows the area where an NMOS transistor will be formed, while the other part indicated by the reference numeral
102
shows the area where a PMOS transistor will be formed. As shown in
FIG. 1A
, a P-type semiconductor substrate
104
is provided, wherein an N-well region
106
is formed. A plurality of field oxide layers
108
are formed on the substrate
104
by local oxidation to define a plurality of active regions of NMOS
100
and PMOS
102
. A gate oxide layer
110
is formed on the substrate
104
by dry oxidation. A polysilicon layer
112
is formed over the substrate
104
by low-pressure chemical vapor deposition (LPCVD). A photolithography process is performed. A patterned photoresist layer
116
a
is formed over the substrate
104
.
As shown in
FIG. 1B
, using the photoresist layer
116
a
as a mask, the polysilicon layer
112
and the oxide layer
110
are subsequently etched to simultaneously form gates
114
a
on the area
100
and gates
114
b
on the area
102
.
As shown in
FIG. 1C
, ion implantation is performed. At first, a photoresist layer
116
b
is formed over the substrate
104
to cover only the area
102
. Using the photoresist layer
116
b
as a mask, an ion implantation is performed on the substrate
104
to form lightly doped regions
118
beside the gates
114
a
in the area
100
. Then, the photoresist layer
116
b
is removed.
As shown in
FIG. 1D
, another photoresist layer
116
c
is then formed over the substrate
104
to cover only the area
100
. Using the photoresist layer
116
c
as a mask, another ion implantation is performed on the substrate
104
to form lightly doped regions
120
beside the gates
114
b
in the area
102
. Then, the photoresist layer
116
c
is removed.
As shown in
FIG. 1E
, spacers
122
are simultaneously formed on sidewalls of the gates
114
a
in the area
100
and the gates
114
b
in the area
102
. Using the spacers
122
as masks, a heavy ion implantation is respectively performed on the substrate
104
to form heavily doped regions in he area
100
and in the area
102
. Consequently, source/drain regions
124
having a lightly doped drain (LDD) structure are respectively formed beside the gates
114
a
and the gates
114
b
. At this step, a CMOS transistor having an NMOS and a PMOS is formed.
Before the gate is formed on the substrate, in order to adjust the difference between the NMOS's threshold voltages and the PMOS's threshold voltages, an ion implantation is performed. One method is to implant phosphorous ions into the polysilicon layer of the gate to adjust the threshold voltages of the NMOS and the PMOS. But this step causes variance in concentration distribution of dopants in the polysilicon layer of NMOS and PMOS. In other words, the dopant concentrations in the polysilicon layer of NMOS and PMOS are different. While the polysilicon layer with different dopant concentrations is etched to simultaneously form gates of NMOS and PMOS, etching rates of NMOS and PMOS are different so that line widths (channel lengths) of NMOS and PMOS generate deviation. At worst, the deviation of NMOS and PMOS allows the line width of the NMOS to achieve the required dimension, but the gate of PMOS is over-etched or bridging occurs between the two gates.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a complementary metal-oxide semiconductor (CMOS). The method can avoid deviation of line widths (channel lengths) of NMOS and PMOS due to the difference of the etching rate caused by concentration distribution of the polysilicon layer. Therefore, over-etching or bridging are further avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a complementary metal-oxide semiconductor (CMOS). A semiconductor substrate is provided wherein the substrate includes a first region with a first conductive type and a second region with a second conductive type. A conductive layer is formed on the substrate. A patterned insulating layer is formed on the conductive layer. A first photoresist layer is formed over the substrate to cover the first region. A portion of the conductive layer on the second region is removed until the substrate is exposed using the insulating layer as a hard mask. A first doping process is performed on the substrate using the first photoresist layer as a mask. The first photoresist layer is removed. A second photoresist layer is formed to cover the second region. A portion of the conductive layer in the first region is removed until the substrate is exposed using the insulating layer as a hard mask. A second doping process is performed on the substrate using the second photoresist layer as a mask. The second photoresist layer is removed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5849615 (1998-12-01), Ahmad et al.

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