Method of combining multilevel memory cells for an error...

Details Method of combining multilevel memory cells for an error... Method of combining multilevel memory cells for an error...

2007-07-10

2007-07-10

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S763000

Reexamination Certificate

active

11183601

ABSTRACT:
A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

REFERENCES:
patent: 6279133 (2001-08-01), Vafai et al.
patent: 6674385 (2004-01-01), Micheloni et al.
patent: 7012835 (2006-03-01), Gonzalez et al.
patent: 7139895 (2006-11-01), Hazama

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