Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-10-30
2001-05-29
Meeks, Timothy (Department: 1762)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S764000, C438S778000, C438S787000, C438S791000, C438S694000, C427S255700, C427S255290, C427S255370, C427S255394, C427S282000
Reexamination Certificate
active
06239040
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87110061, filed Jun. 23, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of coating an amorphous silicon film. More particularly, the present invention relates to a method of coating an amorphous silicon film by a self-aligned process.
2. Description of Related Art
With the steady increase in integrated circuit (IC) density and requirements for low energy consumption in an IC, semiconductor industry is forced to move towards a new art that can manufacture a submicron device. Therefore, a dynamic random access memory (DRAM) with versatile functions causes a great interest. While manufacturing a DRAM, sufficient surface areas are required for the electrodes of storage capacitor to maintain or increase the appropriate electric charge storage. It is particularly a big challenge for DRAM fabrication to store sufficient electric charges on the electrodes for higher integration. The required capacitance can be achieved by close packed storage cells. But with the reducing dimensions of DRAM cells and the close packed capacitors thereof, it is more difficult to store sufficient charges on the capacitors.
The capacitor is the heart of DRAM cells for signal storage. The more charges the capacitor stores, the more signals can be accessed. Therefore, the noises while using amplifiers to read data are obviously reduced. The basic structure of a capacitor is composed of two parallel conductive plates and a dielectric material between these two plates. The capacitance of a capacitor is determined from the dielectric constant of the dielectric material, the surface area of the conductive plates and the thickness of dielectric material. Therefore, the surface area of the conductive plates is increased in order to increase the capacitance. One of the methods for increasing the surface areas of the conductive plates is to form hemispherical grains (HSG) on the conductive plates. The conventional method of forming storage node electrodes using hemispherical grains can increase the capacitance, by which the height and the surface dimension of the electrodes are not required to be increased.
There are several methods of forming hemispherical grains at present. For example, hemispherical grains are directly deposited on a wafer, or a material layer is first deposited on a wafer, the material layer is then annealed to form hemispherical grains. No matter which the manufacturing method is used, amorphous silicon is used as the material forming the hemispherical grains.
Amorphous silicon is commonly applied for thin film transistors and other switch devices. The manufacturing art about the amorphous silicon film in later years is moved towards the purposes of lowering manufacturing capital and increasing qualities of the amorphous silicon film. An amorphous silicon film is formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD is performed to discharge continuously with high frequency or with radio wave frequency, by which silane (SiH
4
) is decomposited to form a hydrogenation amorphous silicon film.
FIGS. 1A
to
1
B are flow charts showing a conventional method of coating an amorphous silicon film. Referring to
FIG. 1A
, a semiconductor substrate
100
is provided. An insulating layer
102
is deposited on the substrate
100
. Openings
10
are formed in the insulating layer
102
. An amorphous silicon layer
12
is deposited to cover the insulating layer
102
and the openings
10
. Referring next to
FIG. 1B
, bottom-electrodes
110
are defined by a photolithography and an etching processes. The feature of the method is to use amorphous silicon as the material of forming the bottom-electrodes. The disadvantage of the method is that an amorphous silicon film applied to nodes with a specific height is restricted because of the very slow deposition rate of an amorphous silicon film. If an amorphous silicon film with larger thickness is deposited to obtain more surface areas, it needs to take three times depositing time of an amorphous silicon layer than a doped polysilicon layer with the same thickness.
FIGS. 2A
to
2
E are flow charts showing another conventional method of covering an amorphous silicon film. Referring to
FIG. 2A
, a semiconductor substrate
200
is provided. An insulating layer
202
is deposited on the substrate
200
. Openings
20
are formed in the insulating layer
202
. A doped polysilicon layer
22
is deposited to cover the insulating layer
202
and the openings
20
. Referring to
FIG. 2B
, an amorphous silicon layer
24
is formed on the doped polysilicon layer
22
. Referring to
FIG. 2C
, the polysilicon layer
22
and the amorphous silicon layer
24
are defined to form the polysilicon layer
26
and the amorphous polysilicon layer
28
by a photolithography process and an etching process. Referring to
FIG. 2D
, an amorphous silicon layer
30
is formed, conformally covering the polysilicon layer
26
and the amorphous silicon layer
28
. Referring to
FIG. 2E
, spacers
32
are formed from the amorphous silicon layer
30
on sidewalls of the polysilicon layer
26
to remove a portion of the amorphous silicon layer
30
, for example, by dry etching. A bottom-electrode
208
is composed of the polysilicon layer
26
, the spacers
32
and the amorphous silicon layer
38
formed after etching. In this method, the feature is that the amorphous silicon film is deposited to form the spacers conformally to the polysilicon blocks. Using the method, it takes less time forming the bottom-electrode. The disadvantage of the method is that the amorphous silicon layer at the corner of the bottom-electrode is thinner, so it causes the bad electricity of the bottom-electrode after etching the amorphous silicon layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method of coating an amorphous silicon film. An amorphous silicon layer is directly deposited by a self-aligned method, therefore, the thickness of the formed film can be controlled accurately. No additional photoresist is used during the whole processes, thereby the duration of performing the process is reduced and a better quality of an amorphous silicon film is obtained. Besides, polysilicon nodes are formed from doped polysilicon to reduce the duration for deposition.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of coating an amorphous silicon film. A semiconductor substrate is provided. A plurality of polysilicon blocks is formed on the substrate. A thin silicon nitride layer is formed to conformally cover the polysilicon blocks. A silicon dioxide layer is formed on the silicon nitride layer to fill vacant spaces between the polysilicon blocks. A polishing process is performed to remove a portion of the silicon dioxide layer to expose the silicon nitride layer. The silicon nitride layer without being covered with the silicon dioxide layer is removed to expose the substrate. An amorphous silicon layer is formed to cover the substrate. A polishing step is performed to remove a portion of the amorphous silicon layer to expose the silicon dioxide layer. The residual silicon dioxide layer and the residual silicon nitride layer is respectively removed, wherein the polysilicon blocks are covered with the amorphous silicon layer. A bottom-electrode is formed from the polysilicon blocks and the amorphous silicon layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5538592 (1996-07-01), Chen et al.
patent: 5837582 (1998-11-01), Su
patent: 5843821 (1998-12-01), Tseng
patent: 5893730 (1999-04-01), Yamazaki et al.
patent: 5897352 (1999-04-01), Lin et al.
Chen Bret
Meeks Timothy
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
LandOfFree
Method of coating amorphous silicon film does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of coating amorphous silicon film, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of coating amorphous silicon film will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2564527